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Abacus turn model-based routing for NoC interconnects with switch or link failures
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FASTER: facilitating analysis and synthesis technologies for effective reconfiguration
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Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor
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Clustered indexing for branch predictors
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A processor-sharing model for input-buffered ATM switches in a correlated traffic environment.
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A quantitative analysis of the benefits of the use of area-I/O pads in FPGAs.
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INTERRUPT REPLAY - A DEBUGGING METHOD FOR PARALLEL PROGRAMS WITH INTERRUPTS.
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A CORRELATION COPROCESSOR FOR ACCURATE REAL-TIME ULTRASONIC RANGING OF MULTIPLE OBJECTS USING THE TRANSPUTER.
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Language coprocessor to support the interpretation of MODULA-2 programs