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- Journal Article
- A1
- open access
Data reuse buffer synthesis using the polyhedral model
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Control for power gating of wires
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Run-time management of a MPSoC containing FPGA fabric tiles
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- Journal Article
- A1
- open access
Systematic simulation-based predictive synthesis of integrated optical interconnect
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Toward the accurate prediction of placement wire length distributions in VLSI circuits
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Improved a priori interconnect predictions and technology extrapolation in the GTX system
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A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
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A priori wire length distribution models with multiterminal nets
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Toward Better Wireload Models in the Presence of Obstacles.
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A stochastic model for the interconnection topology of digital circuits