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- Journal Article
- A1
- open access
Methodology for readout and ring oscillator optimization toward energy-efficient VCO-based ADCs
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- Journal Article
- A1
- open access
The truth about 2-level transition elimination in bang-bang PAM-4 CDRs
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- Journal Article
- A1
- open access
A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit
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- Journal Article
- A1
- open access
A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs
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- Journal Article
- A1
- open access
Analyzing the effect of clock jitter on self-oscillating sigma delta modulators
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- Journal Article
- A1
- open access
Influence of jitter on limit cycles in bang-bang clock and data recovery circuits