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RapidStream 2.0 : automated parallel implementation of latency insensitive FPGA designs through partial reconfiguration
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RWRoute : an open-source timing-driven router for commercial FPGAs
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Accelerating FPGA routing through algorithmic enhancements and connection-aware parallelization
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In-circuit debugging with dynamic reconfiguration of FPGA interconnects
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- Journal Article
- A1
- open access
Identification of dynamic circuit specialization opportunities in RTL code
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On the impact of replacing low-speed configuration buses on FPGAs with the chip’s internal configuration infrastructure