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Applying parameterizable dynamic configurations to sequence alignment
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Developing memory templates for high level synthesis compilers
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- Conference Paper
- P1
- open access
Towards a tighter integration of generated and custom-made hardware
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A parallel for loop memory template for a high level synthesis compiler
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- Conference Paper
- C3
- open access
CLooGVHDL and JCCI
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- Conference Paper
- C1
- open access
Optimizing the FPGA memory design for a Sobel edge detector
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- Conference Paper
- C1
- open access
Optimizing the FPGA memory design for a Sobel edge detector
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Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead
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- Conference Paper
- C1
- open access
Reducing the dynamic FPGA reconfiguration overhead
(2008) p.53-56 -
- Conference Paper
- C1
- open access
Building an Application-specific Memory Hierarchy on FPGA
(2008) p.53-62