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Designing a branch predictor for a block structured architecture
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On the Feasibility of Fixed-Length Block Structured Architectures.
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Performance Analysis through Synthetic Trace Generation
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Estimating IPC of a Block Structured Instruction Set Architecture in an Early Design Stage. Parallel Computing: Fundamentals and Applications ;.
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A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.
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Early design stage exploration of fixed-length block structured architectures.
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On the Benefits of a Block Structured Instruction Set Architecture.
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On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture.
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Investigating the Implementation of a Block Structured Processor Architecture in an Early Design Stage.
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Exploitable levels of ILP in future processors.