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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
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- PhD Thesis
- open access
Techniques for low-overhead dynamic partial reconfiguration of FPGAs
(2015) -
TCONMAP: technology mapping for parameterised FPGA configurations
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On the impact of replacing low-speed configuration buses on FPGAs with the chip’s internal configuration infrastructure
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Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits
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TPaR: place and route tools for the dynamic reconfiguration of the FPGA's interconnect network
(2014) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 33(3). p.370-383 -
- Conference Paper
- P1
- open access
An automatic tool flow for the combined implementation of multi-mode circuits
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- Conference Paper
- C1
- open access
A novel tool flow for increased routing configuration similarity in multi-mode circuits
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- Conference Paper
- P1
- open access
StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs
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- Conference Paper
- C1
- open access
Automating reconfiguration chain generation for SRL-based run-time reconfiguration
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- Conference Paper
- C1
- open access
Memory-efficient and fast run-time reconfiguration of regularly structured designs
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- Conference Paper
- C3
- open access
RecoNoC: a reconfigurable network-on-chip
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Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy