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Exploring large language models for HDL verilog
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Accelerating python numerical libraries using FPGAs
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ZyPy : intercepting NumPy operations for acceleration on FPGAs
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- Conference Paper
- P1
- open access
Empowering parallel computing with field programmable gate arrays
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- Journal Article
- A2
- open access
Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL
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- Conference Paper
- C3
- open access
Exploring Opencl on a CPU-FPGA heterogeneous architecture research platform (HARP)
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- Conference Paper
- P1
- open access
Heterogeneous cloud computing : design methodology to combine hardware accelerators
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- Conference Paper
- C3
- open access
Remote Procedure Call compiler for Field-Programmable Gate Arrays
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- Conference Paper
- C1
- open access
ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs
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Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA
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- Journal Article
- A1
- open access
High-level synthesis optimization for blocked floating-point matrix multiplication
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- Conference Paper
- P1
- open access
ParaFPGA15 : exploring threads and trends in programmable hardware
(2016) PARALLEL COMPUTING : ON THE ROAD TO EXASCALE. In Advances in Parallel Computing 27. p.501-504 -
High-level synthesis for FPGAs, the Swiss army knife for high-performance computing
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- Conference Paper
- P1
- open access
ParaFPGA 2013 : harnessing programs, power and performance in parallel FPGA applications
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Exploiting high-level synthesis tools for high-performance applications on FPGAs