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Tussen practica en Utopia : een vastgoedstrategie voor de lange termijn
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Everything as a service
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Climate change is here to stay, so we'd better prepare for it
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The race for sustainability
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Rethinking education
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The position of Europe in the world
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The race for sovereignty
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EU/US white paper on the continuum of computing
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- Book Chapter
- open access
Taming the IT systems complexity hydra
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- Book Chapter
- open access
AI for a better society
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- Book Chapter
- open access
COVID-19 is more than a pandemic
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- Book Chapter
- open access
Rethinking education
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- Book Chapter
- open access
Europe should be the humans-first continent
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- Book Chapter
- open access
The position of Europe in the world
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- Book Chapter
- open access
Is healthcare ready for a digital future?
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- Book Chapter
- open access
Everything as a service
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Effective and efficient Java‐type obfuscation
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- Journal Article
- A1
- open access
Adaptive compiler strategies for mitigating timing side channel attacks
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Past, present and future of the internet and digitally-augmented humanity : a HiPEAC vision
(2020) -
HiPEAC : a European network built to last
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HiPEAC Vision 2019
(2019) -
HiPEAC Vision 2017
(2017) p.1-167 -
Taming parallelism in a multi-variant execution environment
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Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA
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Evaluation of dynamic binary translation techniques for full system virtualisation on ARMv7-A
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- Conference Paper
- P1
- open access
SOFIA : software and control flow integrity architecture
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- Journal Article
- A1
- open access
Link-time smart card code hardening
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HiPEAC vision 2015
(2015) p.1-65 -
Pushing Java type obfuscation to the limit
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A novel obfuscation: class hierarchy flattening
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- Journal Article
- A1
- open access
Protecting your software updates
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- Journal Article
- A1
- open access
Formal virtualization requirements for the ARM architecture
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GHUMVEE: efficient, effective, and flexible replication
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- Miscellaneous
- open access
The HIPEAC vision for advanced computing in horizon 2020
(2013) p.1-48 -
- Conference Paper
- C1
- open access
Mitigating smart card fault injection with link-time code rewriting: a feasibility study
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Efficient calculation of reduced density matrices from Slater determinant expansions
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Introduction to the special issue on high-performance and embedded architectures and compilers
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DNS tunneling for network penetration
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Automatic parallelization in the paralax compiler
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Whole-array SSA: an intermediate representation of memory for trading-off precision against complexity
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Computing sytems: research challenges ahead: the HiPEAC vision 2011/2012
(2011) p.1-53 -
- Miscellaneous
- open access
Computing systems: research challenges ahead: the HiPEAC Vision 2011/ 2012
(2011) p.1-56 -
Compilation and virtualization in the HiPEAC vision
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A profile-based tool for finding pipeline parallelism in sequential programs
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The paralax infrastructure: automatic parallelization with a helping hand
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- Conference Paper
- C1
- open access
Implicit hints : embedding hint bits in programs without ISA changes
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- Miscellaneous
- open access
The Hipeac Vision, 2010
(2010) p.1-60 -
- Conference Paper
- C1
- open access
An experimental study on performance portability of OpenCL kernels
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System-scenario-based design of dynamic embedded systems
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Practical mitigations for timing-based side-channel attacks
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- Conference Paper
- P1
- open access
Linux kernel compaction through cold code swapping
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Accelerating multiple sequence alignment with the cell BE processor
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- Conference Paper
- C1
- open access
Factoring out ordered sections to expose thread-level parallelism
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- Conference Paper
- C1
- open access
Can we apply accelerator-cores to control-intensive programs?
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Towards automatic program partitioning
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Instruction set limitation in support of software diversity
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Towards Tamper Resistant Code Encryption: Practice and Experience
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Detecting the Existence of Coarse-Grain Parallelism in General-Purpose Programs
(2008) p.1-12 -
A Dynamic Analysis Tool for Finding Coarse-Grain Parallelism
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Extracting Coarse-Grain Parallelism in General-Purpose Programs
(2008) p.281-282 -
Upcoming computing system challenges: the HiPEAC vision
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Behavior-based branch prediction by dynamically clustering branch instructions
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Constructing optimal XOR-functions to minimize cache conflict misses
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Experiences with Parallelizing a Bio-informatics Program on the Cell BE
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Memory footprint reduction for embedded systems
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High-Performance Embedded Architecture and Compilation Roadmap
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- Conference Paper
- C1
- open access
Program Obfuscation: A Quantitative Approach
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- Conference Paper
- C1
- open access
Detection of Coarse-grain Parallelism
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- Conference Paper
- C1
- open access
Whole-Program Linear-Constant Analysis with Applications to Link-Time Optimization
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Architecture and Compilers for Embedded Systems (ACES) Symposium Proceedings
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- Conference Paper
- C1
- open access
Detection of Function-level Parallelism
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A practical interprocedural dominance algorithm
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Java object header elimination for reduced memory consumption in 64-bit virtual machines
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Exploiting program phase behavior for energy reduction on multi-configuration processors
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Clustered indexing for branch predictors
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A model for self-modifying code
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Run-time randomization to mitigate tampering
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- Journal Article
- A2
- open access
Function level parallelism driven by data dependencies
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- Journal Article
- A1
- open access
Using HPM-sampling to drive dynamic compilation
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GCH: hints for triggering garbage collections
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Automated reduction of the memory footprint of the Linux kernel
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Link-time compaction and optimization of ARM executables
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Object-relative addressing: Compressed pointers in 64-bit Java virtual machines
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Exploiting video stream similarity for energy-efficient decoding
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- Journal Article
- A1
- open access
On the expressiveness of timed coordination models
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Bidirectional liveness analysis, or how less than half of the Alpha's registers are used
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64-bit versus 32-bit virtual machines for Java
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Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation
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Improved composite confidence mechanisms for a perceptron branch predictor
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NSL-BLRL: Efficient cache warm'up for sampled processor simulation
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- Conference Paper
- P1
- open access
Space-efficient 64-bit java objects through selective typed virtual addressing
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- Conference Paper
- P1
- open access
An analysis of program phase behavior and its predictability
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- Conference Paper
- P1
- open access
Understanding obfuscated code
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Energy consumption for transport of control information on a segmented software-controlled communication architecture
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- Conference Paper
- C1
- open access
Function Level Parallelism Lead by Data Dependencies
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- Conference Paper
- C1
- open access
NSL-BLRL: Efficient Cache Warmup for Sampled Processor Simulation
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Identifying Program Phase Transition Points
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- Conference Paper
- C1
- open access
Identifying Program Phase Behavior in Parallel Programs on Distributed Shared-memory Systems
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Automatic Generation of Synthetic Benchmarks
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- Conference Paper
- C1
- open access
Classifying Data Dependencies Between Functions
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- Conference Paper
- C1
- open access
Function Level Parallelism Lead by Data Dependencies
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Opaque Predicates Detection by Abstract Interpretation
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- Conference Paper
- C1
- open access
Loco: An Interactive Code (De)Obfuscation tool
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- Conference Paper
- C1
- open access
A Formal Model for Microprocessor Caches
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- Conference Paper
- C1
- open access
Conflict Avoiding Caches Invite New Data Layout Optimizations
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Software protection through dynamic code mutation
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- Conference Paper
- C1
- open access
Microarchitecture-Independent Cache Modeling for Statistical Simulation
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- Conference Paper
- C1
- open access
On the Effectiveness of Source Code Transformations for Binary Obfuscation
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Accurate Memory Data Flow Modeling in Statistical Simulation
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- Conference Paper
- C1
- open access
Opaque Predicates Detection by Abstract Interpretation
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- Conference Paper
- C1
- open access
Identifying the Best Performing Hardware Platform Based on Inherent Program Similarity
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Javana: a system for building customized Java program analysis tools
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- Conference Paper
- C1
- open access
Building Java Program Analysis Tools using Javana
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Using debug information in link-time analysis
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Formally Modeling Microprocessor Caches and Branch Predictors
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Javana: a system for building customized Java program analysis tools
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On the Impact of OS and Linker Effects on Level-2 Cache Performance
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Performance prediction based on inherent program similarity
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Efficient design space exploration of high performance embedded out-of-order processors
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Statistical Simulation of Chip Multiprocessors
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Function Level Parallelism Driven by Data Dependencies
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BLRL: Accurate and efficient warmup for sampled processor simulation
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Optimal sample length for efficient cache simulation
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Link-time binary rewriting techniques for program compaction
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XOR-based hash functions
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DIABLO: a reliable, retargetable and extensible link-time rewriting framework
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The shape of the processor design space and its implications for early stage explorations
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Interference in Branch Predictors: A Systematic Approach
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Steganography for executables and code transformation signatures
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A detailed study on phase predictors
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Offline phase analysis and optimization for multi-configuration processors
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System-wide compaction and specialization of the Linux kernel
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Comparing low-level behavior of SPEC CPU and Java workloads
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Using decision trees to improve program-based and profile-based static branch prediction
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Java objects without the headers
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Calculating the interprocedural dominator relation
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Code (De)Obfuscation
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Program Phase Behavior and Predictability
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The placement of matrices when using XOR-based hashing
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Alignment of matrices when using XOR-based hashing
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Improving Accuracy for Statistical Simulation
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Implicit Typing for 64-bit object header reduction in Java
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Performance Prediction for Java Applications
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Enhanced Statistical Simulation Framework: Accurate Memory Data Flow Model
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Hinting Refactorings to Reduce Object Creation In Java
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Loco: An interactive Code (De)Obfuscation tool
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Garbage collection hints
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LANCET: a nifty code editing tool
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2FAR: A 2bcgskew Predictor Fused by an Alloyed Redundant History Skewed Perceptron Branch Predictor
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Correct Alignment of a Return-Address-Stack after Call and Return Mispredictions
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Backtracking and dynamic patching for free
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Hybrid Static-Dynamic Attacks against Software Protection Mechanisms
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Detecting data races in sequential programs with DIOTA
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Link-time optimization of ARM binaries
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Link-time optimization of IA64 binaries
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Towards an extensible context ontology for ambient intelligence
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On generating set index functions for randomized caches
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JaRec: a portable record/replay environment for multi-threaded Java applications
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Efficient simulation of trace samples on parallel machines
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How accurate should early design stage power/performance tools be? A case study with statistical simulation
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Speeding up architectural simulations for high-performance processors
(2004) SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL. 80(9). p.451-468 -
Efficient architectural design of high performance microprocessors
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Bottleneck Analysis in Java Workloads using Hardware Performance Monitors
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Spotting Java Performance Bottlenecks
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Optimizing a Linux Kernel for Space
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Decision Trees for Improving Heuristic-Based Static Branch Prediction
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Deconstructing and Improving Statistical Simulation in HLS
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Experiments with Subsetting Benchmark Suites
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The Design and Implementation of FIT: a Flexible Instrumentation Toolkit
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Software Piracy Prevention through Diversity
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Eccentric and fragile benchmarks
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Low-level behavioral analysis of the JVT/AVC decoder
(2004) PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). 5308. p.1371-1382 -
Control flow modeling in statistical simulation for accurate and efficient processor design studies
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Evaluation of the Gini-index for studying branch prediction features
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Link-time compaction of MIPS programs
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An efficient data race detector backend for DIOTA
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Trade-offs for skewed-associative caches
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Many Benchmarks Stress the Same Bottlenecks
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Precise Detection of Memory Leaks
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Method-level phase behavior in Java workloads
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Diabatik: Diablo's instrumentation toolkit
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JVM SPEC favours 32-bit platforms
(2003) ProRisc 2003. -
Improved Static Branch Prediction for Weak Dynamic Predictions
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Self-modifying code: instrumentation challenges
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On the use of statistical data analysis techniques in workload characterization
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On the use of statistical data analysis techniques in workload characterization
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Java Programs and Virtual Machines: Observations at the Microarchitectural Level
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Java SPEC favors 32-bit platforms
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Dynamic Techniques for the Optimisation of the Detection of Data Races
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Accurately Warmed-up Trace Samples for the Evaluation of Cache Memories.
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Accurate Replay of Memory Management in Java
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Instrumenting JVM`s at the machine code level
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Investigating the Interaction between Java Programs and Virtual Machines at the Microarchitectural Level
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Java SPEC, designed for 32-bit implementations?
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Improved Static Branch Prediction for Weak Dynamic Predictions
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Diabatik: Diablo's instrumentation toolkit
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Memory Management Replay in DejaVu
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TORNADO: A Novel Input Replay Tool
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Instrumenting self-modifying code
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- Conference Paper
- C1
- open access
Memory Management Replay For DejaVu
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Quantifying the Impact of Input Data Sets on Program Behavior and its Applications
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Selecting a Reduced but Representative Workload
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How Java programs interact with virtual machines at the microarchitectural level
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Record/replay for nondeterministic program executions
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Highly accurate and efficient evaluation of randomising set index functions
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Statistical simulation: Adding efficiency to the computer designer's toolbox
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On the side-effects of code abstraction
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Software techniques for program compaction
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Suspension terms as a means for meta-coordination in the mu Log coordination framework
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Quantifying behavioral differences between multimedia and general-purpose workloads
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Designing computer architecture research workloads
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Randomized caches for power-efficiency
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Debugging shared memory parallel programs using record/replay
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Comparing multiported cache schemes
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- Conference Paper
- P1
- open access
TORNADO : a novel input replay tool
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Efficient microprocessor design space exploration through statistical simulation
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Trace substitution
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Non-Intrusive Detection of Synchronization Errors Using Execution Replay.
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Record/Replay in the Presence of Benign Data Races
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Branch prediction using neural networks.
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Branch Prediction Perspectives using Machine Learning.
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Independent Hashing as Confidence Mechanism for Value Predictors.
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Accurate Statistical Workload Modeling.
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How Input Data Sets Change Program Behaviour.
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Portable record/replay for Java.
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JaRec: a record/replay system for multi-threaded Java applications.
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Investigating the Predictability of Linked Data Structures.
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DIOTA: Dynamic Instrumentation, Optimization and Transformation of Applications
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Software instrumentation using dynamic techniques.
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Optimizing a 3D Image Reconstruction Algorithm: Investigating the Interaction between the High-Level Implementation, the Compiler and the Architecture.
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Evaluation of the Performance of Polynomial Set Index Functions.
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A Comparative Study of Redundancy in Trace Caches.
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Bounding the number of segment histories during data race detection.
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Sifting out the Mud; Low Level C++ Code Reuse.
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Workload design: selecting representative program-input pairs
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An address transformation combining block- and word-interleaving
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TRaDe: Data Race Detection for Java.
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Accordion Clocks: Logical clocks for Data Race Detection.
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Synchronous Coordination in the muLog framework.
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Statistical Simulation of Superscalar Architectures using Commercial Workloads
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Space-Efficient Value Prediction
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Conflict Graph Based Allocation of Objects to Memory Banks.
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Conflict graph based allocation of static objects to memory banks.
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Cyclic Debugging Using Execution Replay.
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JiTI: A Robust Just in Time Instrumentation Technique.
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Blackboard relations in the mu Log coordination model.
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Alto: A Link-Time Optimizer for the Compaq Alpha. Software.
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Combining global code and data compaction.
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Application domains for fixed-length block structured architectures
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Nonuniform behavior in instruction traces for contemporary processors