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A 14-bit 250MS/s digital to analog converter with binary weighted redundant signed digit coding

Benoit Catteau (UGent) , Bart De Vuyst (UGent) , Pieter Rombouts (UGent) and Ludo Weyten (UGent)
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Abstract
It is well known that the performance of current steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch. Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration technique. In this paper we present a D/A converter circuit with a “Redundant Signed Digit” (RSD) coding scheme for binary weighted D/A conversion. This scheme does not really improve the peak performance for full-scale input signals. E.g. with a fullscale 3.2 MHz 14-bit input sinusoidal signal, the SFDR equals 60 dB for our circuit. But the performance is only gradually reduced for small input signals: for a -43 dB 14-bit input signal the SFDR is still 44 dB, which is close to the performance of an ideal 14-bit D/A converter. The analog section of this circuit was implemented in a standard 0.18 mum (1P6M) CMOS process and requires only 0.1 mm^2 of silicon area.
Keywords
Current Steering DAC, Binary Weighted, Digital to Analog, RSD coding scheme

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Chicago
Catteau, Benoit, Bart De Vuyst, Pieter Rombouts, and Ludo Weyten. 2010. “A 14-bit 250MS/s Digital to Analog Converter with Binary Weighted Redundant Signed Digit Coding.” In IEEE International Symposium on Circuits and Systems, 3345–3348. New York, NY, USA: IEEE.
APA
Catteau, B., De Vuyst, B., Rombouts, P., & Weyten, L. (2010). A 14-bit 250MS/s digital to analog converter with binary weighted redundant signed digit coding. IEEE International Symposium on Circuits and Systems (pp. 3345–3348). Presented at the 2010 IEEE International symposium on Circuits and Systems (ISCAS 2010) : Nano-bio circuit fabrics and systems, New York, NY, USA: IEEE.
Vancouver
1.
Catteau B, De Vuyst B, Rombouts P, Weyten L. A 14-bit 250MS/s digital to analog converter with binary weighted redundant signed digit coding. IEEE International Symposium on Circuits and Systems. New York, NY, USA: IEEE; 2010. p. 3345–8.
MLA
Catteau, Benoit, Bart De Vuyst, Pieter Rombouts, et al. “A 14-bit 250MS/s Digital to Analog Converter with Binary Weighted Redundant Signed Digit Coding.” IEEE International Symposium on Circuits and Systems. New York, NY, USA: IEEE, 2010. 3345–3348. Print.
@inproceedings{969744,
  abstract     = {It is well known that the performance of current steering D/A converters (DACs) is affected by parasitic effects such as static device mismatch and dynamic timing mismatch.
Typically, this results into about 10-bit peak performance. To increase this number, the designer has two options: either use a very large silicon area to obtain better matching, or alternatively use a (sophisticated) calibration technique.
In this paper we present a D/A converter circuit with a {\textquotedblleft}Redundant Signed Digit{\textquotedblright} (RSD) coding scheme for binary weighted D/A conversion. This scheme does not really improve the peak performance for full-scale input signals. E.g. with a fullscale 3.2 MHz 14-bit input sinusoidal signal, the SFDR equals 60 dB for our circuit. But the performance is only gradually reduced for small input signals: for a -43 dB 14-bit input signal the SFDR is still 44 dB, which is close to the performance of an ideal 14-bit D/A converter. The analog section of this circuit was implemented in a standard 0.18 mum (1P6M) CMOS process and requires only 0.1 mm\^{ }2 of silicon area.},
  author       = {Catteau, Benoit and De Vuyst, Bart and Rombouts, Pieter and Weyten, Ludo},
  booktitle    = {IEEE International Symposium on Circuits and Systems},
  isbn         = {9781424453085},
  issn         = {0271-4302},
  language     = {eng},
  location     = {Paris, France},
  pages        = {3345--3348},
  publisher    = {IEEE},
  title        = {A 14-bit 250MS/s digital to analog converter with binary weighted redundant signed digit coding},
  url          = {http://dx.doi.org/10.1109/ISCAS.2010.5537880},
  year         = {2010},
}

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