Ghent University Academic Bibliography

Advanced

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

Christof Debaes, Iñigo Artundo, Wim Heirman UGent, Jan Van Campenhout UGent and Hugo Thienpont (2010) Proceedings of SPIE, the International Society for Optical Engineering. 7719.
abstract
There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
Power consumption., Network recon guration, Silicon microrings, Network-on-Chip, Optical interconnects, INTERCONNECTION NETWORKS, OPTICAL NETWORKS, MULTIPROCESSORS, PLATFORM, POWER, NOC
in
Proceedings of SPIE, the International Society for Optical Engineering
Proc. SPIE Int. Soc. Opt. Eng.
editor
Giancarlo C Righini
volume
7719
issue title
Silicon photonics and photonic integrated circuits II
article_number
771916
pages
11 pages
publisher
SPIE, the International Society for Optical Engineering
place of publication
Bellingham, WA, USA
conference name
SPIE Photonics Europe : Silicon photonics and photonic integrated circuits II
conference location
Brussels, Belgium
conference start
2010-04-12
conference end
2010-04-16
Web of Science type
Proceedings Paper
Web of Science id
000285297700029
ISSN
0277-786X
ISBN
9780819481924
DOI
10.1117/12.854744
language
English
UGent publication?
yes
classification
P1
copyright statement
I have transferred the copyright for this publication to the publisher
id
948911
handle
http://hdl.handle.net/1854/LU-948911
date created
2010-05-19 12:11:46
date last changed
2013-07-19 13:59:40
@inproceedings{948911,
  abstract     = {There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35\% reduction) while only generating a modest increase in power consumption (20\%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs.},
  articleno    = {771916},
  author       = {Debaes, Christof and Artundo, I{\~n}igo and Heirman, Wim and Van Campenhout, Jan and Thienpont, Hugo},
  booktitle    = {Proceedings of SPIE, the International Society for Optical Engineering},
  editor       = {Righini, Giancarlo C},
  isbn         = {9780819481924},
  issn         = {0277-786X},
  keyword      = {Power consumption.,Network recon\unmatched{000c}guration,Silicon microrings,Network-on-Chip,Optical interconnects,INTERCONNECTION NETWORKS,OPTICAL NETWORKS,MULTIPROCESSORS,PLATFORM,POWER,NOC},
  language     = {eng},
  location     = {Brussels, Belgium},
  pages        = {11},
  publisher    = {SPIE, the International Society for Optical Engineering},
  title        = {Cycle-accurate evaluation of reconfigurable photonic networks-on-chip},
  url          = {http://dx.doi.org/10.1117/12.854744},
  volume       = {7719},
  year         = {2010},
}

Chicago
Debaes, Christof, Iñigo Artundo, Wim Heirman, Jan Van Campenhout, and Hugo Thienpont. 2010. “Cycle-accurate Evaluation of Reconfigurable Photonic Networks-on-chip.” In Proceedings of SPIE, the International Society for Optical Engineering, ed. Giancarlo C Righini. Vol. 7719. Bellingham, WA, USA: SPIE, the International Society for Optical Engineering.
APA
Debaes, Christof, Artundo, I., Heirman, W., Van Campenhout, J., & Thienpont, H. (2010). Cycle-accurate evaluation of reconfigurable photonic networks-on-chip. In G. C. Righini (Ed.), Proceedings of SPIE, the International Society for Optical Engineering (Vol. 7719). Presented at the SPIE Photonics Europe : Silicon photonics and photonic integrated circuits II, Bellingham, WA, USA: SPIE, the International Society for Optical Engineering.
Vancouver
1.
Debaes C, Artundo I, Heirman W, Van Campenhout J, Thienpont H. Cycle-accurate evaluation of reconfigurable photonic networks-on-chip. In: Righini GC, editor. Proceedings of SPIE, the International Society for Optical Engineering. Bellingham, WA, USA: SPIE, the International Society for Optical Engineering; 2010.
MLA
Debaes, Christof, Iñigo Artundo, Wim Heirman, et al. “Cycle-accurate Evaluation of Reconfigurable Photonic Networks-on-chip.” Proceedings of SPIE, the International Society for Optical Engineering. Ed. Giancarlo C Righini. Vol. 7719. Bellingham, WA, USA: SPIE, the International Society for Optical Engineering, 2010. Print.