@article{8764672,
  abstract     = {{Superscalar out-of-order cores deliver high performance at the cost of increased complexity and power budget. In-order cores, in contrast, are less complex and have a smaller power budget, but offer low performance. A processor architecture should ideally provide high performance in a power- and cost-efficient manner. Recently proposed slice-out-of-order (sOoO) cores identify backward slices of memory operations which they execute out-of-order with respect to the rest of the dynamic instruction stream for increased instruction-level and memory-hierarchy parallelism. Unfortunately, constructing backward slices is imprecise and hardware-inefficient, leaving performance on the table. In this article, we propose Forward Slice Core (FSC), a novel core microarchitecture that builds on a stall-on-use in-order core and extracts more instruction-level and memory-hierarchy parallelism than slice-out-of-order cores. FSC does so by identifying and steering forward slices (rather than backward slices) to dedicated in-order FIFO queues. Moreover, FSC puts load-consumers that depend on L1 D-cache misses on the side to enable younger independent load-consumers to execute faster. Finally, FSC eliminates the need for dynamic memory disambiguation by replicating store-address instructions across queues. Considering 3-wide pipeline configurations, we find that FSC improves performance by 27.1%, 21.1%, and 14.6% on average compared to Freeway, the state-of-the-art sOoO core, across SPEC CPU2017, GAP, and DaCapo, respectively, while at the same time incurring reduced hardware complexity. Compared to an OoO core, FSC reduces power consumption by 61.3% and chip area by 47%, providing a microarchitecture with high performance at low complexity.}},
  articleno    = {{17}},
  author       = {{Lakshminarasimhan, Kartik and Naithani, Ajeya and Feliu, Josue and Eeckhout, Lieven}},
  issn         = {{1544-3566}},
  journal      = {{ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION}},
  keywords     = {{Superscalar microarchitecture,slice-out-of-order,dynamic instruction,scheduling}},
  language     = {{eng}},
  number       = {{2}},
  pages        = {{25}},
  title        = {{The forward slice core : a high-performance, yet low-complexity microarchitecture}},
  url          = {{http://doi.org/10.1145/3499424}},
  volume       = {{19}},
  year         = {{2022}},
}

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