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A low-power reduced kick-back comparator with improved calibration for high-speed flash ADCs

Guy Torfs (UGent) , Zhisheng Li (UGent) , Johan Bauwelinck (UGent) , Xin Yin (UGent) , Jan Vandewege (UGent) and Geert Van der Plas
(2009) IEICE TRANSACTIONS ON ELECTRONICS. E92C(10). p.1328-1330
Author
Organization
Abstract
A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 mu W at 1.8 V power supply and 1 GHz clock frequency.
Keywords
kick-back, comparator, calibration, low-power, flash ADC

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MLA
Torfs, Guy et al. “A Low-power Reduced Kick-back Comparator with Improved Calibration for High-speed Flash ADCs.” IEICE TRANSACTIONS ON ELECTRONICS E92C.10 (2009): 1328–1330. Print.
APA
Torfs, G., Li, Z., Bauwelinck, J., Yin, X., Vandewege, J., & Van der Plas, G. (2009). A low-power reduced kick-back comparator with improved calibration for high-speed flash ADCs. IEICE TRANSACTIONS ON ELECTRONICS, E92C(10), 1328–1330.
Chicago author-date
Torfs, Guy, Zhisheng Li, Johan Bauwelinck, Xin Yin, Jan Vandewege, and Geert Van der Plas. 2009. “A Low-power Reduced Kick-back Comparator with Improved Calibration for High-speed Flash ADCs.” Ieice Transactions on Electronics E92C (10): 1328–1330.
Chicago author-date (all authors)
Torfs, Guy, Zhisheng Li, Johan Bauwelinck, Xin Yin, Jan Vandewege, and Geert Van der Plas. 2009. “A Low-power Reduced Kick-back Comparator with Improved Calibration for High-speed Flash ADCs.” Ieice Transactions on Electronics E92C (10): 1328–1330.
Vancouver
1.
Torfs G, Li Z, Bauwelinck J, Yin X, Vandewege J, Van der Plas G. A low-power reduced kick-back comparator with improved calibration for high-speed flash ADCs. IEICE TRANSACTIONS ON ELECTRONICS. 2009;E92C(10):1328–30.
IEEE
[1]
G. Torfs, Z. Li, J. Bauwelinck, X. Yin, J. Vandewege, and G. Van der Plas, “A low-power reduced kick-back comparator with improved calibration for high-speed flash ADCs,” IEICE TRANSACTIONS ON ELECTRONICS, vol. E92C, no. 10, pp. 1328–1330, 2009.
@article{875292,
  abstract     = {A novel low-power kick-back reduced comparator for use in high-speed flash analog-to-digital converters (ADC) is presented. The proposed comparator combines cascode transistors to reduce the kick-back noise with a built-in threshold voltage to remove the static power consumption of a reference. Without degrading other figures, the kick-back noise is reduced by a factor 8, compared to a previous design without cascode transistors. An improved calibration structure is also proposed to improve linearity when used in an ADC. Simulated in a standard CMOS technology the comparator consumes 106.5 mu W at 1.8 V power supply and 1 GHz clock frequency.},
  author       = {Torfs, Guy and Li, Zhisheng and Bauwelinck, Johan and Yin, Xin and Vandewege, Jan and Van der Plas, Geert},
  issn         = {0916-8524},
  journal      = {IEICE TRANSACTIONS ON ELECTRONICS},
  keywords     = {kick-back,comparator,calibration,low-power,flash ADC},
  language     = {eng},
  number       = {10},
  pages        = {1328--1330},
  title        = {A low-power reduced kick-back comparator with improved calibration for high-speed flash ADCs},
  url          = {http://dx.doi.org/10.1587/transele.E92.C.1328},
  volume       = {E92C},
  year         = {2009},
}

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