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A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies

A. Vais, B. Hsu, O. Syshchyk, H. Yu, A. Alian, Y. Mols, V Kodandarama, K., B. Kunert, N. Waldron, Eddy Simoen (UGent) , et al.
(2021) 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). In International Reliability Physics Symposium
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Abstract
We introduce a set of new characterization techniques for the direct defect analysis of the sidewall surfaces of Nano-ridge, Nanowire, and FinFET based devices, being used in current (and future) logic and RF technologies. We demonstrate the application of these techniques on GaAs mesa, Nano-ridge, and InGaAs nano-wire based PIN diodes where surface defect densities are difficult to extract currently. We show that a close match in extracted density, with both measured data and calibrated TCAD simulations of above device types, is achieved validating the applicability of the techniques.
Keywords
LEVEL TRANSIENT SPECTROSCOPY, RECOMBINATION, TRAPS, III-V, III-V defects, Nano-wire sidewall defects, Nano-ridge devices, Hetero-junction Bipolar transistor

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MLA
Vais, A., et al. “A Defect Characterization Technique for the Sidewall Surface of Nano-Ridge and Nanowire Based Logic and RF Technologies.” 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), Ieee, 2021, doi:10.1109/IRPS46558.2021.9405095.
APA
Vais, A., Hsu, B., Syshchyk, O., Yu, H., Alian, A., Mols, Y., … Collaert, N. (2021). A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies. 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), ELECTR NETWORK. https://doi.org/10.1109/IRPS46558.2021.9405095
Chicago author-date
Vais, A., B. Hsu, O. Syshchyk, H. Yu, A. Alian, Y. Mols, V Kodandarama, K., et al. 2021. “A Defect Characterization Technique for the Sidewall Surface of Nano-Ridge and Nanowire Based Logic and RF Technologies.” In 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). New york: Ieee. https://doi.org/10.1109/IRPS46558.2021.9405095.
Chicago author-date (all authors)
Vais, A., B. Hsu, O. Syshchyk, H. Yu, A. Alian, Y. Mols, V Kodandarama, K., B. Kunert, N. Waldron, Eddy Simoen, and N. Collaert. 2021. “A Defect Characterization Technique for the Sidewall Surface of Nano-Ridge and Nanowire Based Logic and RF Technologies.” In 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). New york: Ieee. doi:10.1109/IRPS46558.2021.9405095.
Vancouver
1.
Vais A, Hsu B, Syshchyk O, Yu H, Alian A, Mols Y, et al. A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies. In: 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). New york: Ieee; 2021.
IEEE
[1]
A. Vais et al., “A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies,” in 2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), ELECTR NETWORK, 2021.
@inproceedings{8752502,
  abstract     = {{We introduce a set of new characterization techniques for the direct defect analysis of the sidewall surfaces of Nano-ridge, Nanowire, and FinFET based devices, being used in current (and future) logic and RF technologies. We demonstrate the application of these techniques on GaAs mesa, Nano-ridge, and InGaAs nano-wire based PIN diodes where surface defect densities are difficult to extract currently. We show that a close match in extracted density, with both measured data and calibrated TCAD simulations of above device types, is achieved validating the applicability of the techniques.}},
  author       = {{Vais, A. and Hsu, B. and Syshchyk, O. and Yu, H. and Alian, A. and Mols, Y. and Kodandarama, K., V and Kunert, B. and Waldron, N. and Simoen, Eddy and Collaert, N.}},
  booktitle    = {{2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)}},
  isbn         = {{9781728168937}},
  issn         = {{1541-7026}},
  keywords     = {{LEVEL TRANSIENT SPECTROSCOPY,RECOMBINATION,TRAPS,III-V,III-V defects,Nano-wire sidewall defects,Nano-ridge devices,Hetero-junction Bipolar transistor}},
  language     = {{eng}},
  location     = {{ELECTR NETWORK}},
  pages        = {{5}},
  publisher    = {{Ieee}},
  title        = {{A defect characterization technique for the sidewall surface of Nano-ridge and Nanowire based Logic and RF technologies}},
  url          = {{http://doi.org/10.1109/IRPS46558.2021.9405095}},
  year         = {{2021}},
}
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