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An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS

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Abstract
A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2-4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of 430 mu W is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.
Keywords
INJECTION-LOCKING, Digital transmitter, IEEE 802154a, IEEE 802154z, impulse radio, localization, polar transmitter, transversal filter, ultra-wideband, (UWB)

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Citation

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MLA
Singh, Gaurav, et al. “An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 56, no. 12, 2021, pp. 3799–810, doi:10.1109/JSSC.2021.3116895.
APA
Singh, G., Allebes, E., He, Y., Tiurin, E., Mateman, P., Dijkhuis, J. F., … Liu, Y.-H. (2021). An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 56(12), 3799–3810. https://doi.org/10.1109/JSSC.2021.3116895
Chicago author-date
Singh, Gaurav, Erwin Allebes, Yuming He, Evgenii Tiurin, Paul Mateman, Johan F. Dijkhuis, Gert-Jan van Schaik, et al. 2021. “An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 56 (12): 3799–3810. https://doi.org/10.1109/JSSC.2021.3116895.
Chicago author-date (all authors)
Singh, Gaurav, Erwin Allebes, Yuming He, Evgenii Tiurin, Paul Mateman, Johan F. Dijkhuis, Gert-Jan van Schaik, Elbert Bechthum, Johan van den Heuvel, Mohieddine El Soussi, Arjan Breeschoten, Hannu Korpela, Gert-Jan Gordebeke, Sam Lemey, Christian Bachmann, and Yao-Hong Liu. 2021. “An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-Nm CMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 56 (12): 3799–3810. doi:10.1109/JSSC.2021.3116895.
Vancouver
1.
Singh G, Allebes E, He Y, Tiurin E, Mateman P, Dijkhuis JF, et al. An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2021;56(12):3799–810.
IEEE
[1]
G. Singh et al., “An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 56, no. 12, pp. 3799–3810, 2021.
@article{8730934,
  abstract     = {{A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2-4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of 430 mu W is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.}},
  author       = {{Singh, Gaurav and Allebes, Erwin and He, Yuming and Tiurin, Evgenii and Mateman, Paul and Dijkhuis, Johan F. and van Schaik, Gert-Jan and Bechthum, Elbert and van den Heuvel, Johan and El Soussi, Mohieddine and Breeschoten, Arjan and Korpela, Hannu and Gordebeke, Gert-Jan and Lemey, Sam and Bachmann, Christian and Liu, Yao-Hong}},
  issn         = {{0018-9200}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  keywords     = {{INJECTION-LOCKING,Digital transmitter,IEEE 802154a,IEEE 802154z,impulse radio,localization,polar transmitter,transversal filter,ultra-wideband,(UWB)}},
  language     = {{eng}},
  number       = {{12}},
  pages        = {{3799--3810}},
  title        = {{An IR-UWB IEEE 802.15.4z compatible coherent asynchronous polar transmitter in 28-nm CMOS}},
  url          = {{http://doi.org/10.1109/JSSC.2021.3116895}},
  volume       = {{56}},
  year         = {{2021}},
}

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