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A 100-GS/s four-to-one analog time interleaver in 55-nm SiGe BiCMOS

Hannes Ramon, Michiel Verplaetse (UGent) , Michael Vanhoecke (UGent) , Haolin Li (UGent) , Johan Bauwelinck (UGent) , Peter Ossieur (UGent) , Xin Yin (UGent) and Guy Torfs (UGent)
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Abstract
We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.
Keywords
DAC, TRANSMITTER, CONVERTERS, FREQUENCY, ADCS, Clocks, Bandwidth, BiCMOS integrated circuits, Silicon germanium, Mixers, Gain, Equalizers, 100 GS, s, BiCMOS, digital-to-analog, equalizer, interleaver, return-to-zero (RZ)

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Citation

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MLA
Ramon, Hannes, et al. “A 100-GS/s Four-to-One Analog Time Interleaver in 55-Nm SiGe BiCMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 56, no. 8, 2021, pp. 2539–49, doi:10.1109/JSSC.2021.3057575.
APA
Ramon, H., Verplaetse, M., Vanhoecke, M., Li, H., Bauwelinck, J., Ossieur, P., … Torfs, G. (2021). A 100-GS/s four-to-one analog time interleaver in 55-nm SiGe BiCMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 56(8), 2539–2549. https://doi.org/10.1109/JSSC.2021.3057575
Chicago author-date
Ramon, Hannes, Michiel Verplaetse, Michael Vanhoecke, Haolin Li, Johan Bauwelinck, Peter Ossieur, Xin Yin, and Guy Torfs. 2021. “A 100-GS/s Four-to-One Analog Time Interleaver in 55-Nm SiGe BiCMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 56 (8): 2539–49. https://doi.org/10.1109/JSSC.2021.3057575.
Chicago author-date (all authors)
Ramon, Hannes, Michiel Verplaetse, Michael Vanhoecke, Haolin Li, Johan Bauwelinck, Peter Ossieur, Xin Yin, and Guy Torfs. 2021. “A 100-GS/s Four-to-One Analog Time Interleaver in 55-Nm SiGe BiCMOS.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 56 (8): 2539–2549. doi:10.1109/JSSC.2021.3057575.
Vancouver
1.
Ramon H, Verplaetse M, Vanhoecke M, Li H, Bauwelinck J, Ossieur P, et al. A 100-GS/s four-to-one analog time interleaver in 55-nm SiGe BiCMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2021;56(8):2539–49.
IEEE
[1]
H. Ramon et al., “A 100-GS/s four-to-one analog time interleaver in 55-nm SiGe BiCMOS,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 56, no. 8, pp. 2539–2549, 2021.
@article{8719554,
  abstract     = {{We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.}},
  author       = {{Ramon, Hannes and Verplaetse, Michiel and Vanhoecke, Michael and Li, Haolin and Bauwelinck, Johan and Ossieur, Peter and Yin, Xin and Torfs, Guy}},
  issn         = {{0018-9200}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  keywords     = {{DAC,TRANSMITTER,CONVERTERS,FREQUENCY,ADCS,Clocks,Bandwidth,BiCMOS integrated circuits,Silicon germanium,Mixers,Gain,Equalizers,100 GS,s,BiCMOS,digital-to-analog,equalizer,interleaver,return-to-zero (RZ)}},
  language     = {{eng}},
  number       = {{8}},
  pages        = {{2539--2549}},
  title        = {{A 100-GS/s four-to-one analog time interleaver in 55-nm SiGe BiCMOS}},
  url          = {{http://dx.doi.org/10.1109/JSSC.2021.3057575}},
  volume       = {{56}},
  year         = {{2021}},
}

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