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A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS

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Abstract
Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of >100 Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to >100 Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach >100 Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain >100 Gbaud operation with a large amount of filter taps in a compact configuration.

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MLA
Verplaetse, Michiel, et al. “A 4-to-1 240 Gb/s PAM-4 MUX with a 7-Tap Mixed-Signal FFE in 55nm BiCMOS.” 2021 IEEE Custom Integrated Circuits Conference (CICC), Proceedings, IEEE, 2021, doi:10.1109/cicc51472.2021.9431514.
APA
Verplaetse, M., Ramon, H., Singh, N., Moeneclaey, B., Ossieur, P., & Torfs, G. (2021). A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS. 2021 IEEE Custom Integrated Circuits Conference (CICC), Proceedings. Presented at the IEEE CICC2021, the Custom Integrated Circuits Conference, Austin, TX, USA. https://doi.org/10.1109/cicc51472.2021.9431514
Chicago author-date
Verplaetse, Michiel, Hannes Ramon, Nishant Singh, Bart Moeneclaey, Peter Ossieur, and Guy Torfs. 2021. “A 4-to-1 240 Gb/s PAM-4 MUX with a 7-Tap Mixed-Signal FFE in 55nm BiCMOS.” In 2021 IEEE Custom Integrated Circuits Conference (CICC), Proceedings. IEEE. https://doi.org/10.1109/cicc51472.2021.9431514.
Chicago author-date (all authors)
Verplaetse, Michiel, Hannes Ramon, Nishant Singh, Bart Moeneclaey, Peter Ossieur, and Guy Torfs. 2021. “A 4-to-1 240 Gb/s PAM-4 MUX with a 7-Tap Mixed-Signal FFE in 55nm BiCMOS.” In 2021 IEEE Custom Integrated Circuits Conference (CICC), Proceedings. IEEE. doi:10.1109/cicc51472.2021.9431514.
Vancouver
1.
Verplaetse M, Ramon H, Singh N, Moeneclaey B, Ossieur P, Torfs G. A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS. In: 2021 IEEE Custom Integrated Circuits Conference (CICC), proceedings. IEEE; 2021.
IEEE
[1]
M. Verplaetse, H. Ramon, N. Singh, B. Moeneclaey, P. Ossieur, and G. Torfs, “A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS,” in 2021 IEEE Custom Integrated Circuits Conference (CICC), proceedings, Austin, TX, USA, 2021.
@inproceedings{8708761,
  abstract     = {{Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of >100 Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to >100 Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach >100 Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain >100 Gbaud operation with a large amount of filter taps in a compact configuration.}},
  author       = {{Verplaetse, Michiel and Ramon, Hannes and Singh, Nishant and Moeneclaey, Bart and Ossieur, Peter and Torfs, Guy}},
  booktitle    = {{2021 IEEE Custom Integrated Circuits Conference (CICC), proceedings}},
  isbn         = {{9781728175812}},
  issn         = {{2152-3630}},
  language     = {{eng}},
  location     = {{Austin, TX, USA}},
  pages        = {{2}},
  publisher    = {{IEEE}},
  title        = {{A 4-to-1 240 Gb/s PAM-4 MUX with a 7-tap mixed-signal FFE in 55nm BiCMOS}},
  url          = {{http://doi.org/10.1109/cicc51472.2021.9431514}},
  year         = {{2021}},
}

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