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VNF-AAPC : accelerator-aware VNF placement and chaining

Gourav Prateek Sharma (UGent) , Wouter Tavernier (UGent) , Didier Colle (UGent) and Mario Pickavet (UGent)
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Abstract
In recent years, telecom operators have been migrating towards network architectures based on Network Function Virtualization in order to reduce their high Capital Expenditure (CAPEX) and Operational Expenditure (OPEX). However, virtualization of some network functions is accompanied by a significant degradation of Virtual Network Function (VNF) performance in terms of their throughput or energy consumption. To address these challenges, use of hardware-accelerators, e.g. FPGAs, GPUs, to offload CPU-intensive operations from performance-critical VNFs has been proposed. Allocation of NFV infrastructure (NFVi) resources for VNF placement and chaining (VNF-PC) has been a major area of research recently. A variety of resources allocation models have been proposed to achieve various operator's objectives i.e. minimizing CAPEX, OPEX, latency, etc. However, the VNF-PC resource allocation problem for the case when NFVi incorporates hardware-accelerators remains unaddressed. Ignoring hardware-accelerators in NFVi while performing resource allocation for VNF-chains can nullify the advantages resulting from the use of hardware-accelerators. Therefore, accurate models and techniques for the accelerator-aware VNF-PC (VNF-AAPC) are needed in order to achieve the overall efficient utilization of all NFVi resources including hardware-accelerators. This paper investigates the problem of VNF-AAPC, i.e., how to allocate usual NFVi resources along-with hardware-accelerators to VNF-chains in a cost-efficient manner. Particularly, we propose two methods to tackle the VNF-AAPC problem. The first approach is based on Integer Linear Programming (ILP) which jointly optimizes VNF placement, chaining and accelerator allocation while concurring to all NFVi constraints. The second approach is a heuristic-based method that addresses the scalability issue of the ILP approach. The heuristic addresses the VNF-AAPC problem by following a two-step algorithm. The experimental evaluations indicate that incorporating accelerator-awareness in VNF-PC strategies can help operators to achieve additional cost-savings from the efficient allocation of hardware-accelerator resources.
Keywords
Hardware-Accelerators, NFV, VNF, Placement, Chaining, Allocation, FPGA, GPU

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MLA
Sharma, Gourav Prateek, et al. “VNF-AAPC : Accelerator-Aware VNF Placement and Chaining.” COMPUTER NETWORKS, vol. 177, Elsevier, 2020, doi:10.1016/j.comnet.2020.107329.
APA
Sharma, G. P., Tavernier, W., Colle, D., & Pickavet, M. (2020). VNF-AAPC : accelerator-aware VNF placement and chaining. COMPUTER NETWORKS, 177. https://doi.org/10.1016/j.comnet.2020.107329
Chicago author-date
Sharma, Gourav Prateek, Wouter Tavernier, Didier Colle, and Mario Pickavet. 2020. “VNF-AAPC : Accelerator-Aware VNF Placement and Chaining.” COMPUTER NETWORKS 177. https://doi.org/10.1016/j.comnet.2020.107329.
Chicago author-date (all authors)
Sharma, Gourav Prateek, Wouter Tavernier, Didier Colle, and Mario Pickavet. 2020. “VNF-AAPC : Accelerator-Aware VNF Placement and Chaining.” COMPUTER NETWORKS 177. doi:10.1016/j.comnet.2020.107329.
Vancouver
1.
Sharma GP, Tavernier W, Colle D, Pickavet M. VNF-AAPC : accelerator-aware VNF placement and chaining. COMPUTER NETWORKS. 2020;177.
IEEE
[1]
G. P. Sharma, W. Tavernier, D. Colle, and M. Pickavet, “VNF-AAPC : accelerator-aware VNF placement and chaining,” COMPUTER NETWORKS, vol. 177, 2020.
@article{8670738,
  abstract     = {In recent years, telecom operators have been migrating towards network architectures based on Network Function Virtualization in order to reduce their high Capital Expenditure (CAPEX) and Operational Expenditure (OPEX). However, virtualization of some network functions is accompanied by a significant degradation of Virtual Network Function (VNF) performance in terms of their throughput or energy consumption. To address these challenges, use of hardware-accelerators, e.g. FPGAs, GPUs, to offload CPU-intensive operations from performance-critical VNFs has been proposed. Allocation of NFV infrastructure (NFVi) resources for VNF placement and chaining (VNF-PC) has been a major area of research recently. A variety of resources allocation models have been proposed to achieve various operator's objectives i.e. minimizing CAPEX, OPEX, latency, etc. However, the VNF-PC resource allocation problem for the case when NFVi incorporates hardware-accelerators remains unaddressed. Ignoring hardware-accelerators in NFVi while performing resource allocation for VNF-chains can nullify the advantages resulting from the use of hardware-accelerators. Therefore, accurate models and techniques for the accelerator-aware VNF-PC (VNF-AAPC) are needed in order to achieve the overall efficient utilization of all NFVi resources including hardware-accelerators. This paper investigates the problem of VNF-AAPC, i.e., how to allocate usual NFVi resources along-with hardware-accelerators to VNF-chains in a cost-efficient manner. Particularly, we propose two methods to tackle the VNF-AAPC problem. The first approach is based on Integer Linear Programming (ILP) which jointly optimizes VNF placement, chaining and accelerator allocation while concurring to all NFVi constraints. The second approach is a heuristic-based method that addresses the scalability issue of the ILP approach. The heuristic addresses the VNF-AAPC problem by following a two-step algorithm. The experimental evaluations indicate that incorporating accelerator-awareness in VNF-PC strategies can help operators to achieve additional cost-savings from the efficient allocation of hardware-accelerator resources.},
  articleno    = {107329},
  author       = {Sharma, Gourav Prateek and Tavernier, Wouter and Colle, Didier and Pickavet, Mario},
  issn         = {1389-1286},
  journal      = {COMPUTER NETWORKS},
  keywords     = {Hardware-Accelerators,NFV,VNF,Placement,Chaining,Allocation,FPGA,GPU},
  language     = {eng},
  pages        = {17},
  publisher    = {Elsevier},
  title        = {VNF-AAPC : accelerator-aware VNF placement and chaining},
  url          = {http://dx.doi.org/10.1016/j.comnet.2020.107329},
  volume       = {177},
  year         = {2020},
}

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