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Empowering parallel computing with field programmable gate arrays

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Abstract
After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements.
Keywords
FPGAs, high-level synthesis, high-performance computing, design space exploration, field programmable gate arrays, HLS, parallel computing, fallacies, pitfalls

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MLA
D’Hollander, Erik. “Empowering Parallel Computing with Field Programmable Gate Arrays.” International Conference on Parallel Computing (ParCo 2019), Proceedings, edited by Ian Foster et al., vol. 36, IOS Press, 2020, pp. 16–31, doi:10.3233/APC200020.
APA
D’Hollander, E. (2020). Empowering parallel computing with field programmable gate arrays. In I. Foster, G. R. Joubert, L. Kučera, W. E. Nagel, & F. Peters (Eds.), International Conference on Parallel Computing (ParCo 2019), Proceedings (Vol. 36, pp. 16–31). Prague, Czech Republic: IOS Press. https://doi.org/10.3233/APC200020
Chicago author-date
D’Hollander, Erik. 2020. “Empowering Parallel Computing with Field Programmable Gate Arrays.” In International Conference on Parallel Computing (ParCo 2019), Proceedings, edited by Ian Foster, Gerhard R. Joubert, Luděk Kučera, Wolfgang E. Nagel, and Frans Peters, 36:16–31. IOS Press. https://doi.org/10.3233/APC200020.
Chicago author-date (all authors)
D’Hollander, Erik. 2020. “Empowering Parallel Computing with Field Programmable Gate Arrays.” In International Conference on Parallel Computing (ParCo 2019), Proceedings, ed by. Ian Foster, Gerhard R. Joubert, Luděk Kučera, Wolfgang E. Nagel, and Frans Peters, 36:16–31. IOS Press. doi:10.3233/APC200020.
Vancouver
1.
D’Hollander E. Empowering parallel computing with field programmable gate arrays. In: Foster I, Joubert GR, Kučera L, Nagel WE, Peters F, editors. International Conference on Parallel Computing (ParCo 2019), Proceedings. IOS Press; 2020. p. 16–31.
IEEE
[1]
E. D’Hollander, “Empowering parallel computing with field programmable gate arrays,” in International Conference on Parallel Computing (ParCo 2019), Proceedings, Prague, Czech Republic, 2020, vol. 36, pp. 16–31.
@inproceedings{8655665,
  abstract     = {After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements.},
  author       = {D'Hollander, Erik},
  booktitle    = {International Conference on Parallel Computing (ParCo 2019), Proceedings},
  editor       = {Foster, Ian and Joubert, Gerhard R. and Kučera, Luděk and Nagel, Wolfgang E. and Peters, Frans},
  isbn         = {9781643680705},
  issn         = {0927-5452},
  keywords     = {FPGAs,high-level synthesis,high-performance computing,design space exploration,field programmable gate arrays,HLS,parallel computing,fallacies,pitfalls},
  language     = {eng},
  location     = {Prague, Czech Republic},
  pages        = {16--31},
  publisher    = {IOS Press},
  title        = {Empowering parallel computing with field programmable gate arrays},
  url          = {http://dx.doi.org/10.3233/APC200020},
  volume       = {36},
  year         = {2020},
}

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