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3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI

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Abstract
In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm(2) ) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55 mu m wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.
Keywords
Silicon photonic interposer, through silicon via (TSV), electronic-photonic integrated circuits (EPIC), packaging, Cu pillars, thermocomompression bonding, data center, optical switch, optical interconnects, heterogeneous integration

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MLA
Sirbu, Bogdan, et al. “3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical through Silicon via on SOI.” 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), IEEE, 2019, pp. 1052–59.
APA
Sirbu, B., Eichhammer, Y., Oppermann, H., Tekin, T., Kraft, J., Sidorov, V., … Soares, F. (2019). 3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI. In 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) (pp. 1052–1059). Las Vegas, USA: IEEE.
Chicago author-date
Sirbu, Bogdan, Yann Eichhammer, Hermann Oppermann, Tolga Tekin, Jochen Kraft, Victor Sidorov, Xin Yin, Johan Bauwelinck, Christian Neumeyr, and Francisco Soares. 2019. “3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical through Silicon via on SOI.” In 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 1052–59. IEEE.
Chicago author-date (all authors)
Sirbu, Bogdan, Yann Eichhammer, Hermann Oppermann, Tolga Tekin, Jochen Kraft, Victor Sidorov, Xin Yin, Johan Bauwelinck, Christian Neumeyr, and Francisco Soares. 2019. “3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical through Silicon via on SOI.” In 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 1052–1059. IEEE.
Vancouver
1.
Sirbu B, Eichhammer Y, Oppermann H, Tekin T, Kraft J, Sidorov V, et al. 3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI. In: 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC). IEEE; 2019. p. 1052–9.
IEEE
[1]
B. Sirbu et al., “3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI,” in 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), Las Vegas, USA, 2019, pp. 1052–1059.
@inproceedings{8643688,
  abstract     = {{In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm(2) ) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55 mu m wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.}},
  author       = {{Sirbu, Bogdan and Eichhammer, Yann and Oppermann, Hermann and Tekin, Tolga and Kraft, Jochen and Sidorov, Victor and Yin, Xin and Bauwelinck, Johan and Neumeyr, Christian and Soares, Francisco}},
  booktitle    = {{2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)}},
  isbn         = {{9781728114996}},
  keywords     = {{Silicon photonic interposer,through silicon via (TSV),electronic-photonic integrated circuits (EPIC),packaging,Cu pillars,thermocomompression bonding,data center,optical switch,optical interconnects,heterogeneous integration}},
  language     = {{eng}},
  location     = {{Las Vegas, USA}},
  pages        = {{1052--1059}},
  publisher    = {{IEEE}},
  title        = {{3D silicon photonics interposer for Tb/s optical interconnects in data centers with double-side assembled active components and integrated optical and electrical through silicon via on SOI}},
  url          = {{http://dx.doi.org/10.1109/ectc.2019.00165}},
  year         = {{2019}},
}

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