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Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL

(2019) ALGORITHMS. 12(8).
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Abstract
Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second.
Keywords
Reconfigurable computing, High Performance Computing, FPGA, OpenCL, Theoretical Computer Science, Computational Theory and Mathematics, Numerical Analysis, Computational Mathematics, field-programmable gate arrays, OpenCL, high-performance computing, guided image filter, DESIGN

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Citation

Please use this url to cite or link to this publication:

MLA
Faict, Thomas, et al. “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” ALGORITHMS, vol. 12, no. 8, 2019, doi:10.3390/a12080149.
APA
Faict, T., D’Hollander, E., & Goossens, B. (2019). Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL. ALGORITHMS, 12(8). https://doi.org/10.3390/a12080149
Chicago author-date
Faict, Thomas, Erik D’Hollander, and Bart Goossens. 2019. “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” ALGORITHMS 12 (8). https://doi.org/10.3390/a12080149.
Chicago author-date (all authors)
Faict, Thomas, Erik D’Hollander, and Bart Goossens. 2019. “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” ALGORITHMS 12 (8). doi:10.3390/a12080149.
Vancouver
1.
Faict T, D’Hollander E, Goossens B. Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL. ALGORITHMS. 2019;12(8).
IEEE
[1]
T. Faict, E. D’Hollander, and B. Goossens, “Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL,” ALGORITHMS, vol. 12, no. 8, 2019.
@article{8634914,
  abstract     = {Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second.},
  articleno    = {149},
  author       = {Faict, Thomas and D'Hollander, Erik and Goossens, Bart},
  issn         = {1999-4893},
  journal      = {ALGORITHMS},
  keywords     = {Reconfigurable computing,High Performance Computing,FPGA,OpenCL,Theoretical Computer Science,Computational Theory and Mathematics,Numerical Analysis,Computational Mathematics,field-programmable gate arrays,OpenCL,high-performance computing,guided image filter,DESIGN},
  language     = {eng},
  number       = {8},
  pages        = {24},
  title        = {Mapping a guided image filter on the HARP reconfigurable architecture using OpenCL},
  url          = {http://dx.doi.org/10.3390/a12080149},
  volume       = {12},
  year         = {2019},
}

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