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Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs

Dries Vercaemer (UGent) , Johan Raman (UGent) and Pieter Rombouts (UGent)
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Abstract
In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slowing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, stewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable.
Keywords
DELTA-SIGMA MODULATORS, CLOCK JITTER, DESIGN TECHNIQUES, COMPENSATION, Analog-to-digital conversion, pulse-width modulation, small area ADC, CTSDM, low power, SC-DAC

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MLA
Vercaemer, Dries, et al. “Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 66, no. 4, Ieee-inst Electrical Electronics Engineers Inc, 2019, pp. 1369–81.
APA
Vercaemer, D., Raman, J., & Rombouts, P. (2019). Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66(4), 1369–1381.
Chicago author-date
Vercaemer, Dries, Johan Raman, and Pieter Rombouts. 2019. “Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 66 (4): 1369–81.
Chicago author-date (all authors)
Vercaemer, Dries, Johan Raman, and Pieter Rombouts. 2019. “Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 66 (4): 1369–1381.
Vancouver
1.
Vercaemer D, Raman J, Rombouts P. Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2019;66(4):1369–81.
IEEE
[1]
D. Vercaemer, J. Raman, and P. Rombouts, “Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 66, no. 4, pp. 1369–1381, 2019.
@article{8627811,
  abstract     = {In this paper, a technique is introduced that improves the performance of one-bit continuous-time sigma delta modulators (CTSDMs) using a low-pass filtering switched capacitor digital to analog converter (LPSC-DAC). This DAC effectively combines an infinite impulse response filter with a switched capacitor resistor DAC (SCR-DAC). The resulting DAC is inherently immune toward inter-symbol interference. Moreover, by filtering the feedback signal in the discrete-time domain, the jitter robustness of the modulator is greatly improved and most importantly the slowing requirements on the OpAmps in the modulator's loop filter are greatly relaxed up to a level that the OpAmps can be scaled down toward their ultimate noise limited power level. Furthermore, this LPSC-DAC does not suffer from the SCR-DAC's disadvantageous trade-off between the modulator's jitter, stewing, and anti-aliasing performance. We also show how to compensate for the extra pole of the LPSC-DAC, such that the CTSDM's loop filter, noise- and signal-transfer function remains unchanged. As a result, this technique is completely transparent to the system level designer and established system-level design techniques for sigma delta modulators remain applicable.},
  author       = {Vercaemer, Dries and Raman, Johan and Rombouts, Pieter},
  issn         = {1549-8328},
  journal      = {IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS},
  keywords     = {DELTA-SIGMA MODULATORS,CLOCK JITTER,DESIGN TECHNIQUES,COMPENSATION,Analog-to-digital conversion,pulse-width modulation,small area ADC,CTSDM,low power,SC-DAC},
  language     = {eng},
  number       = {4},
  pages        = {1369--1381},
  publisher    = {Ieee-inst Electrical Electronics Engineers Inc},
  title        = {Low-pass filtering SC-DAC for reduced jitter and slewing requirements on CTSDMs},
  url          = {http://dx.doi.org/10.1109/TCSI.2018.2882746},
  volume       = {66},
  year         = {2019},
}

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