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A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs

Haolin Li (UGent) , Laurens Breyne (UGent) , Joris Van Kerrebrouck (UGent) , Michiel Verplaetse (UGent) , Chia-Yi Wu (UGent) , Piet Demeester (UGent) and Guy Torfs (UGent)
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ATTO (A new concept for ultra-high capacity wireless networks)
Abstract
A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a single-bit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the designs of wideband software defined radio transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520-MHz baseband bandwidth with 42.76-dB signal-to-noise-and-distortion ratio (SNDR) or 1.1-GHz bandwidth with 32.04-dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75MBd 256 QAM over 200-m OM4 multimode fiber in real time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.
Keywords
RADIO, DAC, Delta-sigma modulator, multi-stage noise shaping (MASH), software, defined radio, quantization noise, FPGA

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Citation

Please use this url to cite or link to this publication:

MLA
Li, Haolin et al. “A 21-GS/s Single-bit Second-order Delta-sigma Modulator for FPGAs.” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 66.3 (2019): 482–486. Print.
APA
Li, Haolin, Breyne, L., Van Kerrebrouck, J., Verplaetse, M., Wu, C.-Y., Demeester, P., & Torfs, G. (2019). A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 66(3), 482–486.
Chicago author-date
Li, Haolin, Laurens Breyne, Joris Van Kerrebrouck, Michiel Verplaetse, Chia-Yi Wu, Piet Demeester, and Guy Torfs. 2019. “A 21-GS/s Single-bit Second-order Delta-sigma Modulator for FPGAs.” Ieee Transactions on Circuits and Systems Ii-express Briefs 66 (3): 482–486.
Chicago author-date (all authors)
Li, Haolin, Laurens Breyne, Joris Van Kerrebrouck, Michiel Verplaetse, Chia-Yi Wu, Piet Demeester, and Guy Torfs. 2019. “A 21-GS/s Single-bit Second-order Delta-sigma Modulator for FPGAs.” Ieee Transactions on Circuits and Systems Ii-express Briefs 66 (3): 482–486.
Vancouver
1.
Li H, Breyne L, Van Kerrebrouck J, Verplaetse M, Wu C-Y, Demeester P, et al. A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS. IEEE; 2019;66(3):482–6.
IEEE
[1]
H. Li et al., “A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 66, no. 3, pp. 482–486, 2019.
@article{8608810,
  abstract     = {A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a single-bit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the designs of wideband software defined radio transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520-MHz baseband bandwidth with 42.76-dB signal-to-noise-and-distortion ratio (SNDR) or 1.1-GHz bandwidth with 32.04-dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75MBd 256 QAM over 200-m OM4 multimode fiber in real time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.},
  author       = {Li, Haolin and Breyne, Laurens and Van Kerrebrouck, Joris and Verplaetse, Michiel and Wu, Chia-Yi and Demeester, Piet and Torfs, Guy},
  issn         = {1549-7747},
  journal      = {IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS},
  keywords     = {RADIO,DAC,Delta-sigma modulator,multi-stage noise shaping (MASH),software,defined radio,quantization noise,FPGA},
  language     = {eng},
  number       = {3},
  pages        = {482--486},
  publisher    = {IEEE},
  title        = {A 21-GS/s single-bit second-order delta-sigma modulator for FPGAs},
  url          = {http://dx.doi.org/10.1109/TCSII.2018.2855962},
  volume       = {66},
  year         = {2019},
}

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