Advanced search
1 file | 1.92 MB Add to list

Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping

Author
Organization
Abstract
Recently an architecture for a nearly digital VCO ADC with high order quantization noise shaping was presented. Unfortunately, the structure is affected by the non-linearity of the first VCO. In this manuscript, we report experimental results of a potential solution for this problem: placing a pulse width modulator (PWM) in front of this first VCO. The work is based on a prototype VCO-ADC with 3rd order noise shaping and 10 MHz bandwidth, implemented in a 65 nm CMOS technology. For small input signals the circuit behaves as expected. Unfortunately for larger input signal levels the noise of the prototype is significantly higher than was expected from the a priori simulations. Upon investigation, this is attributed to subtle (mismatch induced) intermodulation effects. Overall the prototype's measured performance leads to a DR/SNR/SNDR of 67.4/59/55.4 dB at a 10MHz bandwidth while consuming 2.3mW from a 1.0V analog and 2mW from a 1.2V digital supply.
Keywords
DELTA-SIGMA ADC, BANDWIDTH, DESIGN, FOM, analog-to-digital conversion, oversampling, time encoding, voltage, controlled oscillator

Downloads

  • (...).pdf
    • full text
    • |
    • UGent only
    • |
    • PDF
    • |
    • 1.92 MB

Citation

Please use this url to cite or link to this publication:

MLA
Babaie Fishani, Amir, et al. “Experimental Results on PWM Linearization of a VCO-ADC with 3rd Order Noise Shaping.” 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE, 2018, doi:10.1109/ISCAS.2018.8351694.
APA
Babaie Fishani, A., Vercaemer, D., Raman, J., & Rombouts, P. (2018). Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping. 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). Presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY. https://doi.org/10.1109/ISCAS.2018.8351694
Chicago author-date
Babaie Fishani, Amir, Dries Vercaemer, Johan Raman, and Pieter Rombouts. 2018. “Experimental Results on PWM Linearization of a VCO-ADC with 3rd Order Noise Shaping.” In 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). New york: IEEE. https://doi.org/10.1109/ISCAS.2018.8351694.
Chicago author-date (all authors)
Babaie Fishani, Amir, Dries Vercaemer, Johan Raman, and Pieter Rombouts. 2018. “Experimental Results on PWM Linearization of a VCO-ADC with 3rd Order Noise Shaping.” In 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). New york: IEEE. doi:10.1109/ISCAS.2018.8351694.
Vancouver
1.
Babaie Fishani A, Vercaemer D, Raman J, Rombouts P. Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping. In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). New york: IEEE; 2018.
IEEE
[1]
A. Babaie Fishani, D. Vercaemer, J. Raman, and P. Rombouts, “Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping,” in 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Florence, ITALY, 2018.
@inproceedings{8590195,
  abstract     = {{Recently an architecture for a nearly digital VCO ADC with high order quantization noise shaping was presented. Unfortunately, the structure is affected by the non-linearity of the first VCO. In this manuscript, we report experimental results of a potential solution for this problem: placing a pulse width modulator (PWM) in front of this first VCO. The work is based on a prototype VCO-ADC with 3rd order noise shaping and 10 MHz bandwidth, implemented in a 65 nm CMOS technology. For small input signals the circuit behaves as expected. Unfortunately for larger input signal levels the noise of the prototype is significantly higher than was expected from the a priori simulations. Upon investigation, this is attributed to subtle (mismatch induced) intermodulation effects. Overall the prototype's measured performance leads to a DR/SNR/SNDR of 67.4/59/55.4 dB at a 10MHz bandwidth while consuming 2.3mW from a 1.0V analog and 2mW from a 1.2V digital supply.}},
  author       = {{Babaie Fishani, Amir and Vercaemer, Dries and Raman, Johan and Rombouts, Pieter}},
  booktitle    = {{2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)}},
  isbn         = {{9781538648810}},
  issn         = {{0271-4302}},
  keywords     = {{DELTA-SIGMA ADC,BANDWIDTH,DESIGN,FOM,analog-to-digital conversion,oversampling,time encoding,voltage,controlled oscillator}},
  language     = {{eng}},
  location     = {{Florence, ITALY}},
  pages        = {{5}},
  publisher    = {{IEEE}},
  title        = {{Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping}},
  url          = {{http://doi.org/10.1109/ISCAS.2018.8351694}},
  year         = {{2018}},
}

Altmetric
View in Altmetric
Web of Science
Times cited: