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Comparator hysteresis compensation for decision feedback equalisers

(2018) ELECTRONICS LETTERS. 54(25). p.1421-1422
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Abstract
High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.
Keywords
compensation, decision feedback equalisers, hysteresis, comparators, (circuits), decision feedback equaliser, serial link receiver designs, bit error rate, decision margin, equaliser coefficient adaptation, scheme, comparator input voltage architectures, high-speed comparator, hysteresis compensation strategy, multilevel modulations, binary, modulations

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Citation

Please use this url to cite or link to this publication:

MLA
Mattia, O. E. et al. “Comparator Hysteresis Compensation for Decision Feedback Equalisers.” ELECTRONICS LETTERS 54.25 (2018): 1421–1422. Print.
APA
Mattia, O. E., Guermandi, D., Torfs, G., & Wambacq, P. (2018). Comparator hysteresis compensation for decision feedback equalisers. ELECTRONICS LETTERS, 54(25), 1421–1422.
Chicago author-date
Mattia, O. E., D. Guermandi, Guy Torfs, and P. Wambacq. 2018. “Comparator Hysteresis Compensation for Decision Feedback Equalisers.” Electronics Letters 54 (25): 1421–1422.
Chicago author-date (all authors)
Mattia, O. E., D. Guermandi, Guy Torfs, and P. Wambacq. 2018. “Comparator Hysteresis Compensation for Decision Feedback Equalisers.” Electronics Letters 54 (25): 1421–1422.
Vancouver
1.
Mattia OE, Guermandi D, Torfs G, Wambacq P. Comparator hysteresis compensation for decision feedback equalisers. ELECTRONICS LETTERS. Hertford: Inst Engineering Technology-iet; 2018;54(25):1421–2.
IEEE
[1]
O. E. Mattia, D. Guermandi, G. Torfs, and P. Wambacq, “Comparator hysteresis compensation for decision feedback equalisers,” ELECTRONICS LETTERS, vol. 54, no. 25, pp. 1421–1422, 2018.
@article{8587745,
  abstract     = {High-speed comparators are extensively used in serial link receiver designs. Some comparator architectures can show significant hysteresis that degrade the sensitivity of the receiver, increasing the bit error rate. In this Letter, a comparator hysteresis compensation strategy that re-uses the first tap of a decision feedback equaliser to shift the comparator input voltage, increasing the decision margin is proposed. An updated equaliser coefficient adaptation scheme is also introduced. The proposed technique can be used for binary and multi-level modulations.},
  author       = {Mattia, O. E. and Guermandi, D. and Torfs, Guy and Wambacq, P.},
  issn         = {0013-5194},
  journal      = {ELECTRONICS LETTERS},
  keywords     = {compensation,decision feedback equalisers,hysteresis,comparators,(circuits),decision feedback equaliser,serial link receiver designs,bit error rate,decision margin,equaliser coefficient adaptation,scheme,comparator input voltage architectures,high-speed comparator,hysteresis compensation strategy,multilevel modulations,binary,modulations},
  language     = {eng},
  number       = {25},
  pages        = {1421--1422},
  publisher    = {Inst Engineering Technology-iet},
  title        = {Comparator hysteresis compensation for decision feedback equalisers},
  url          = {http://dx.doi.org/10.1049/el.2018.6485},
  volume       = {54},
  year         = {2018},
}

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