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Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs

Alexandra Kourfali, Dirk Stroobandt (UGent) and David Merodio Codinachs
(2017) Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs.
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Abstract
Reassuring fault tolerance in computing systems is the most important problem for mission critical space com- ponents. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded an on- demand three level fault-mitigation technique tailored for FPGA overlays. The proposed method performs run-time recovery via Microscrubbing. This approach can achieve up to 3× faster run- time recovery with 10.2× less resources in FPGA devices, by providing integrated layers of fault mitigation.

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MLA
Kourfali, Alexandra, et al. “Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs.” Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs, IEEE, 2017.
APA
Kourfali, A., Stroobandt, D., & Merodio Codinachs, D. (2017). Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs. In Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs. CERN, Geneva: IEEE.
Chicago author-date
Kourfali, Alexandra, Dirk Stroobandt, and David Merodio Codinachs. 2017. “Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs.” In Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs. IEEE.
Chicago author-date (all authors)
Kourfali, Alexandra, Dirk Stroobandt, and David Merodio Codinachs. 2017. “Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs.” In Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs. IEEE.
Vancouver
1.
Kourfali A, Stroobandt D, Merodio Codinachs D. Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs. In: Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs. IEEE; 2017.
IEEE
[1]
A. Kourfali, D. Stroobandt, and D. Merodio Codinachs, “Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs,” in Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs, CERN, Geneva, 2017.
@inproceedings{8583694,
  abstract     = {{Reassuring fault tolerance in computing systems is the most important problem for mission critical space com- ponents. With the rise in interest of commercial SRAM-based FPGAs, it is crucial to provide runtime reconfigurable recovery from a failure. In this paper we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded an on- demand three level fault-mitigation technique tailored for FPGA overlays. The proposed method performs run-time recovery via Microscrubbing. This approach can achieve up to 3× faster run- time recovery with 10.2× less resources in FPGA devices, by providing integrated layers of fault mitigation.}},
  author       = {{Kourfali, Alexandra and Stroobandt, Dirk and Merodio Codinachs, David}},
  booktitle    = {{Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs}},
  language     = {{eng}},
  location     = {{CERN, Geneva}},
  pages        = {{5}},
  publisher    = {{IEEE}},
  title        = {{Superimposed In-circuit fault mitigation for dynamically reconfigurable FPGAs}},
  url          = {{http://radecs2017.com/Radecs2017/assets/images/PocketProgram.pdf}},
  year         = {{2017}},
}