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Abacus turn model-based routing for NoC interconnects with switch or link failures

Poona Bahrebar UGent and Dirk Stroobandt UGent (2018) MICROPROCESSORS AND MICROSYSTEMS. 59. p.69-91
abstract
With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient routing methods is of significant importance. Most of the existing fault-tolerant techniques rely on rerouting solutions which may degrade the network performance drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, such off-line techniques cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and deadlock-free routing method is proposed based on the Abacus Turn Model (AbTM) to tolerate single and double switch or link failures. The required resources are kept to a minimum by avoiding to use virtual channels and routing tables. The proposed method is able to dynamically adjust the availability of the healthy paths according to the location of failures and congestion in the network to minimize rerouting. Moreover, it can grant a high degree of adaptiveness to the packets. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs. The experimental results demonstrate that an 8  ×  8 mesh network remains 100% reliable against single faults, and 99.8% and 99.94% reliable against double switch and link failures, respectively.
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
keyword
Network-on-Chip (NoC), Fault-tolerant routing methods, Deadlock, Abacus Turn Model (AbTM), Reconfiguration
journal title
MICROPROCESSORS AND MICROSYSTEMS
volume
59
pages
23 pages
publisher
Elsevier Ltd.
ISSN
0141-9331
DOI
https://doi.org/10.1016/j.micpro.2018.01.005
language
English
UGent publication?
yes
classification
U
id
8561950
handle
http://hdl.handle.net/1854/LU-8561950
alternative location
https://www.sciencedirect.com/science/article/pii/S0141933117301734
date created
2018-05-15 15:17:50
date last changed
2018-05-15 15:24:04
@article{8561950,
  abstract     = {With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient routing methods is of significant importance. Most of the existing fault-tolerant techniques rely on rerouting solutions which may degrade the network performance drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, such off-line techniques cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and deadlock-free routing method is proposed based on the Abacus Turn Model (AbTM) to tolerate single and double switch or link failures. The required resources are kept to a minimum by avoiding to use virtual channels and routing tables. The proposed method is able to dynamically adjust the availability of the healthy paths according to the location of failures and congestion in the network to minimize rerouting. Moreover, it can grant a high degree of adaptiveness to the packets. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs. The experimental results demonstrate that an 8\unmatched{202f}\unmatched{202f}{\texttimes}\unmatched{202f}\unmatched{202f}8 mesh network remains 100\% reliable against single faults, and 99.8\% and 99.94\% reliable against double switch and link failures, respectively.},
  author       = {Bahrebar, Poona and Stroobandt, Dirk},
  issn         = {0141-9331},
  journal      = {MICROPROCESSORS AND MICROSYSTEMS},
  keyword      = {Network-on-Chip (NoC),Fault-tolerant routing methods,Deadlock,Abacus Turn Model (AbTM),Reconfiguration},
  language     = {eng},
  pages        = {69--91},
  publisher    = {Elsevier Ltd.},
  title        = {Abacus turn model-based routing for NoC interconnects with switch or link failures},
  url          = {http://dx.doi.org/https://doi.org/10.1016/j.micpro.2018.01.005},
  volume       = {59},
  year         = {2018},
}

Chicago
Bahrebar, Poona, and Dirk Stroobandt. 2018. “Abacus Turn Model-based Routing for NoC Interconnects with Switch or Link Failures.” Microprocessors and Microsystems 59: 69–91.
APA
Bahrebar, P., & Stroobandt, D. (2018). Abacus turn model-based routing for NoC interconnects with switch or link failures. MICROPROCESSORS AND MICROSYSTEMS, 59, 69–91.
Vancouver
1.
Bahrebar P, Stroobandt D. Abacus turn model-based routing for NoC interconnects with switch or link failures. MICROPROCESSORS AND MICROSYSTEMS. Elsevier Ltd.; 2018;59:69–91.
MLA
Bahrebar, Poona, and Dirk Stroobandt. “Abacus Turn Model-based Routing for NoC Interconnects with Switch or Link Failures.” MICROPROCESSORS AND MICROSYSTEMS 59 (2018): 69–91. Print.