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How preserving circuit design hierarchy during FPGA packing leads to better performance

Dries Vercruyce (UGent) , Elias Vansteenkiste (UGent) and Dirk Stroobandt (UGent)
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Keywords
Design hierarchy, field-programmable gate array (FPGA), packing, partitioning

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Citation

Please use this url to cite or link to this publication:

MLA
Vercruyce, Dries, et al. “How Preserving Circuit Design Hierarchy during FPGA Packing Leads to Better Performance.” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 37, no. 3, 2018, pp. 629–42.
APA
Vercruyce, D., Vansteenkiste, E., & Stroobandt, D. (2018). How preserving circuit design hierarchy during FPGA packing leads to better performance. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(3), 629–642.
Chicago author-date
Vercruyce, Dries, Elias Vansteenkiste, and Dirk Stroobandt. 2018. “How Preserving Circuit Design Hierarchy during FPGA Packing Leads to Better Performance.” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 37 (3): 629–42.
Chicago author-date (all authors)
Vercruyce, Dries, Elias Vansteenkiste, and Dirk Stroobandt. 2018. “How Preserving Circuit Design Hierarchy during FPGA Packing Leads to Better Performance.” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 37 (3): 629–642.
Vancouver
1.
Vercruyce D, Vansteenkiste E, Stroobandt D. How preserving circuit design hierarchy during FPGA packing leads to better performance. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2018;37(3):629–42.
IEEE
[1]
D. Vercruyce, E. Vansteenkiste, and D. Stroobandt, “How preserving circuit design hierarchy during FPGA packing leads to better performance,” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 37, no. 3, pp. 629–642, 2018.
@article{8558609,
  author       = {Vercruyce, Dries and Vansteenkiste, Elias and Stroobandt, Dirk},
  issn         = {0278-0070},
  journal      = {IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS},
  keywords     = {Design hierarchy,field-programmable gate array (FPGA),packing,partitioning},
  language     = {eng},
  number       = {3},
  pages        = {629--642},
  title        = {How preserving circuit design hierarchy during FPGA packing leads to better performance},
  url          = {http://dx.doi.org/10.1109/tcad.2017.2717786},
  volume       = {37},
  year         = {2018},
}

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