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A 40 MHz-BW 12-bit continuous-time a dagger I pound modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS

Xinpeng Xing, Maarten De Bock, Pieter Rombouts UGent and Georges Gielen (2015) ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. 84(1). p.137-148
abstract
A 4th-order 40 MHz-BW 12-bit continuous-time delta-sigma modulator with digital calibration is presented. A cost-efficient current-shaping technique for the SC DAC is proposed to relax the OTA slewing requirement. The DAC static and dynamic mismatches are eliminated by a look-up table based digital calibration. With a 1.2 V power supply and a 960 MHz clock, 73.6 dB peak SNR and 76.3 dB DR are measured for a 40 MHz bandwidth. After calibration, the modulator achieves an excellent SFDR of 84.2 dB and a 72.9 dB peak SNDR, with IM3 better than 85 dB. The modulator consumes 69.6 mW power, and occupies 0.28 mm(2) area in 90 nm CMOS.
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
keyword
CT DSM, LUT-based Calibration, Shaped SC DAC, Doublet
journal title
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
volume
84
issue
1
pages
137 - 148
publisher
SPRINGER
Web of Science id
000355333800014
ISBN
{0925-1030}
DOI
10.1007/s10470-015-0561-8
language
English
UGent publication?
yes
classification
A1
copyright statement
I have transferred the copyright for this publication to the publisher
id
8558418
handle
http://hdl.handle.net/1854/LU-8558418
date created
2018-04-05 10:28:39
date last changed
2018-05-15 12:35:04
@article{8558418,
  abstract     = {A 4th-order 40 MHz-BW 12-bit continuous-time delta-sigma modulator with digital calibration is presented. A cost-efficient current-shaping technique for the SC DAC is proposed to relax the OTA slewing requirement. The DAC static and dynamic mismatches are eliminated by a look-up table based digital calibration. With a 1.2 V power supply and a 960 MHz clock, 73.6 dB peak SNR and 76.3 dB DR are measured for a 40 MHz bandwidth. After calibration, the modulator achieves an excellent SFDR of 84.2 dB and a 72.9 dB peak SNDR, with IM3 better than 85 dB. The modulator consumes 69.6 mW power, and occupies 0.28 mm(2) area in 90 nm CMOS.},
  author       = {Xing, Xinpeng and De Bock, Maarten and Rombouts, Pieter and Gielen, Georges},
  isbn         = {\{0925-1030\}},
  journal      = {ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING},
  keyword      = {CT DSM,LUT-based Calibration,Shaped SC DAC,Doublet},
  language     = {eng},
  number       = {1},
  pages        = {137--148},
  publisher    = {SPRINGER},
  title        = {A 40 MHz-BW 12-bit continuous-time a dagger I pound modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS},
  url          = {http://dx.doi.org/10.1007/s10470-015-0561-8},
  volume       = {84},
  year         = {2015},
}

Chicago
Xing, Xinpeng, Maarten De Bock, Pieter Rombouts, and Georges Gielen. 2015. “A 40 MHz-BW 12-bit Continuous-time a Dagger I Pound Modulator with Digital Calibration and 84.2 dB-SFDR in 90 Nm CMOS.” Analog Integrated Circuits and Signal Processing 84 (1): 137–148.
APA
Xing, X., De Bock, M., Rombouts, P., & Gielen, G. (2015). A 40 MHz-BW 12-bit continuous-time a dagger I pound modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 84(1), 137–148.
Vancouver
1.
Xing X, De Bock M, Rombouts P, Gielen G. A 40 MHz-BW 12-bit continuous-time a dagger I pound modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. SPRINGER; 2015;84(1):137–48.
MLA
Xing, Xinpeng, Maarten De Bock, Pieter Rombouts, et al. “A 40 MHz-BW 12-bit Continuous-time a Dagger I Pound Modulator with Digital Calibration and 84.2 dB-SFDR in 90 Nm CMOS.” ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 84.1 (2015): 137–148. Print.