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Efficient parallelization of polyphase arbitrary resampling FIR filters for high-speed applications

Hannes Ramon (UGent) , Haolin Li (UGent) , Piet Demeester (UGent) , Johan Bauwelinck (UGent) and Guy Torfs (UGent)
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Abstract
This article describes a method for increasing the sampling rate of efficient polyphase arbitrary resampling FIR filters. An FPGA proof of concept prototype of this architecture has been implemented in a Xilinx Kintex-7 FPGA which is able to convert the sampling rate of a signal from 500 MHz to 600 MHz. This article compares this new architecture with other best known efficient resampling architectures implemented on the same FPGA. The area usage on the FPGA shows that our proposed implementation is very proficient in high bandwidth applications without requiring significantly more resources on the FPGA. A theoretical calculation of the resampling error introduced on a modulated data stream is provided to evaluate the new architecture against other existing resampling architectures.
Keywords
FIR, FPGA, Polyphase filter, Resampling, Broadband, IBCN

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Please use this url to cite or link to this publication:

Chicago
Ramon, Hannes, Haolin Li, Piet Demeester, Johan Bauwelinck, and Guy Torfs. 2018. “Efficient Parallelization of Polyphase Arbitrary Resampling FIR Filters for High-speed Applications.” Journal of Signal Processing Systems for Signal Image and Video Technology 90 (3): 295–303.
APA
Ramon, H., Li, H., Demeester, P., Bauwelinck, J., & Torfs, G. (2018). Efficient parallelization of polyphase arbitrary resampling FIR filters for high-speed applications. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 90(3), 295–303.
Vancouver
1.
Ramon H, Li H, Demeester P, Bauwelinck J, Torfs G. Efficient parallelization of polyphase arbitrary resampling FIR filters for high-speed applications. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY. New york: Springer; 2018;90(3):295–303.
MLA
Ramon, Hannes et al. “Efficient Parallelization of Polyphase Arbitrary Resampling FIR Filters for High-speed Applications.” JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 90.3 (2018): 295–303. Print.
@article{8556950,
  abstract     = {This article describes a method for increasing the sampling rate of efficient polyphase arbitrary resampling FIR filters. An FPGA proof of concept prototype of this architecture has been implemented in a Xilinx Kintex-7 FPGA which is able to convert the sampling rate of a signal from 500 MHz to 600 MHz. This article compares this new architecture with other best known efficient resampling architectures implemented on the same FPGA. The area usage on the FPGA shows that our proposed implementation is very proficient in high bandwidth applications without requiring significantly more resources on the FPGA. A theoretical calculation of the resampling error introduced on a modulated data stream is provided to evaluate the new architecture against other existing resampling architectures.},
  author       = {Ramon, Hannes and Li, Haolin and Demeester, Piet and Bauwelinck, Johan and Torfs, Guy},
  issn         = {1939-8018},
  journal      = {JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY},
  keywords     = {FIR,FPGA,Polyphase filter,Resampling,Broadband,IBCN},
  language     = {eng},
  number       = {3},
  pages        = {295--303},
  publisher    = {Springer},
  title        = {Efficient parallelization of polyphase arbitrary resampling FIR filters for high-speed applications},
  url          = {http://dx.doi.org/10.1007/s11265-017-1235-9},
  volume       = {90},
  year         = {2018},
}

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