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A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs

Marijn Verbeke (UGent) , Pieter Rombouts (UGent) , Hannes Ramon (UGent) , Jochem Verbist (UGent) , Johan Bauwelinck (UGent) , Xin Yin (UGent) and Guy Torfs (UGent)
(2018) JOURNAL OF LIGHTWAVE TECHNOLOGY. 36(8). p.1503-1509
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Abstract
The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to extract a synchronous clock and recover the received data. To achieve a sufficiently fast settling time for 25 Gb/s burst mode upstream applications in passive optical networks (PONs), we introduce an architecture of the first 25 Gb/s all-digital clock and data recovery circuit (AD-CDR). Thanks to the implementation of a digital loop filter, our AD-CDR avoids the need of a system clock or a start-of-burst signal. This circuit is implemented in a 40-nm CMOS process and has a very compact active chip area of only 0.050 mm(2). Furthermore, the performance of the burst-mode operation of our AD-CDR in an optical setup is measured and reported, resulting in a burst-mode lock time of 37.5 ns and consuming only 46 mW.
Keywords
NETWORKS, JITTER, All-digital clock and data recovery (AD-CDR), burst mode, continuous, mode, digital loop filter, inverse alexander phase detector, NG-EPON, passive optical network (PON), PLL-based CDR, quarter-rate ring, oscillator, subsampling

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MLA
Verbeke, Marijn et al. “A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs.” JOURNAL OF LIGHTWAVE TECHNOLOGY 36.8 (2018): 1503–1509. Print.
APA
Verbeke, Marijn, Rombouts, P., Ramon, H., Verbist, J., Bauwelinck, J., Yin, X., & Torfs, G. (2018). A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs. JOURNAL OF LIGHTWAVE TECHNOLOGY, 36(8), 1503–1509.
Chicago author-date
Verbeke, Marijn, Pieter Rombouts, Hannes Ramon, Jochem Verbist, Johan Bauwelinck, Xin Yin, and Guy Torfs. 2018. “A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs.” Journal of Lightwave Technology 36 (8): 1503–1509.
Chicago author-date (all authors)
Verbeke, Marijn, Pieter Rombouts, Hannes Ramon, Jochem Verbist, Johan Bauwelinck, Xin Yin, and Guy Torfs. 2018. “A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs.” Journal of Lightwave Technology 36 (8): 1503–1509.
Vancouver
1.
Verbeke M, Rombouts P, Ramon H, Verbist J, Bauwelinck J, Yin X, et al. A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs. JOURNAL OF LIGHTWAVE TECHNOLOGY. Piscataway: Ieee-inst Electrical Electronics Engineers Inc; 2018;36(8):1503–9.
IEEE
[1]
M. Verbeke et al., “A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs,” JOURNAL OF LIGHTWAVE TECHNOLOGY, vol. 36, no. 8, pp. 1503–1509, 2018.
@article{8555827,
  abstract     = {The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to extract a synchronous clock and recover the received data. To achieve a sufficiently fast settling time for 25 Gb/s burst mode upstream applications in passive optical networks (PONs), we introduce an architecture of the first 25 Gb/s all-digital clock and data recovery circuit (AD-CDR). Thanks to the implementation of a digital loop filter, our AD-CDR avoids the need of a system clock or a start-of-burst signal. This circuit is implemented in a 40-nm CMOS process and has a very compact active chip area of only 0.050 mm(2). Furthermore, the performance of the burst-mode operation of our AD-CDR in an optical setup is measured and reported, resulting in a burst-mode lock time of 37.5 ns and consuming only 46 mW.},
  author       = {Verbeke, Marijn and Rombouts, Pieter and Ramon, Hannes and Verbist, Jochem and Bauwelinck, Johan and Yin, Xin and Torfs, Guy},
  issn         = {0733-8724},
  journal      = {JOURNAL OF LIGHTWAVE TECHNOLOGY},
  keywords     = {NETWORKS,JITTER,All-digital clock and data recovery (AD-CDR),burst mode,continuous,mode,digital loop filter,inverse alexander phase detector,NG-EPON,passive optical network (PON),PLL-based CDR,quarter-rate ring,oscillator,subsampling},
  language     = {eng},
  number       = {8},
  pages        = {1503--1509},
  publisher    = {Ieee-inst Electrical Electronics Engineers Inc},
  title        = {A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs},
  url          = {http://dx.doi.org/10.1109/JLT.2017.2784848},
  volume       = {36},
  year         = {2018},
}

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