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ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs

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Abstract
The biennial mini-symposium “Parallel computing with FPGAs” brings together research on applications and tools fostering the use of field programmable gate arrays. Key aspects are the efficiency, programmability, scalability and portability of high-level synthesis languages and tools. In particular this year's contributions present productivity and programmability results of using HLS languages OpenCL, OmpSs, MATLAB/Octave, OpenSPL and Vivado HLS. The current state and future challenges of HLS within the FPGA landscape is covered in a special keynote on bridging the gap between software and hardware designers.
Keywords
field programmable gate arrays, high-level synthesis, ParaFPGA

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Chicago
D’Hollander, Erik, and Abdellah Touhafi. 2018. “ParaFPGA 2017 : Enlarging the Scope of Parallel Programming with FPGAs.” In International Conference on Parallel Computing (ParCo) 2017, ed. Sanzio Bassini, Marco Danelutto, Patrizio Dazzi, Gerhard R. Joubert, and Frans Peters, 32:619–621. Amsterdam: IOS Press.
APA
D’Hollander, E., & Touhafi, A. (2018). ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs. In S. Bassini, M. Danelutto, P. Dazzi, G. R. Joubert, & F. Peters (Eds.), International Conference on Parallel Computing (ParCo) 2017 (Vol. 32, pp. 619–621). Presented at the International Conference on Parallel Computing, Amsterdam: IOS Press.
Vancouver
1.
D’Hollander E, Touhafi A. ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs. In: Bassini S, Danelutto M, Dazzi P, Joubert GR, Peters F, editors. International Conference on Parallel Computing (ParCo) 2017. Amsterdam: IOS Press; 2018. p. 619–21.
MLA
D’Hollander, Erik, and Abdellah Touhafi. “ParaFPGA 2017 : Enlarging the Scope of Parallel Programming with FPGAs.” International Conference on Parallel Computing (ParCo) 2017. Ed. Sanzio Bassini et al. Vol. 32. Amsterdam: IOS Press, 2018. 619–621. Print.
@inproceedings{8551211,
  abstract     = {The biennial mini-symposium {\textquotedblleft}Parallel computing with FPGAs{\textquotedblright} brings together research on applications and tools fostering the use of field programmable gate arrays. Key aspects are the efficiency, programmability, scalability and portability of high-level synthesis languages and tools. In particular this year's contributions present productivity and programmability results of using HLS languages OpenCL, OmpSs, MATLAB/Octave, OpenSPL and Vivado HLS. The current state and future challenges of HLS within the FPGA landscape is covered in a special keynote on bridging the gap between software and hardware designers.},
  author       = {D'Hollander, Erik and Touhafi, Abdellah},
  booktitle    = {International Conference on Parallel Computing (ParCo) 2017},
  editor       = {Bassini, Sanzio and Danelutto, Marco and Dazzi, Patrizio and Joubert, Gerhard R.  and Peters, Frans},
  isbn         = { 978-1-61499-842-6},
  keyword      = {field programmable gate arrays,high-level synthesis,ParaFPGA},
  language     = {eng},
  location     = {Bologna, Italy},
  pages        = {619--621},
  publisher    = {IOS Press},
  title        = {ParaFPGA 2017 : enlarging the scope of parallel programming with FPGAs},
  url          = {http://ebooks.iospress.nl/volumearticle/48658},
  volume       = {32},
  year         = {2018},
}