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A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit

Marijn Verbeke (UGent) , Pieter Rombouts (UGent) , Hannes Ramon (UGent) , Bart Moeneclaey (UGent) , Xin Yin (UGent) , Johan Bauwelinck (UGent) and Guy Torfs (UGent)
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Abstract
Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm(2) and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive.
Keywords
IBCN, BANG-BANG CLOCK, 28 NM CMOS, SENSE-AMPLIFIER, FLIP-FLOP, CDR, DESIGN, JITTER, ADC, PON, All-digital clock and data recovery (AD-CDR), digital controlled, oscillator (DCO), digital loop filter (DLF), Inverse Alexander phase, detector (PD), subsampling, synthesis

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Citation

Please use this url to cite or link to this publication:

MLA
Verbeke, Marijn et al. “A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-digital Clock and Data Recovery Circuit.” IEEE JOURNAL OF SOLID-STATE CIRCUITS 53.2 (2018): 470–483. Print.
APA
Verbeke, Marijn, Rombouts, P., Ramon, H., Moeneclaey, B., Yin, X., Bauwelinck, J., & Torfs, G. (2018). A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 53(2), 470–483.
Chicago author-date
Verbeke, Marijn, Pieter Rombouts, Hannes Ramon, Bart Moeneclaey, Xin Yin, Johan Bauwelinck, and Guy Torfs. 2018. “A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-digital Clock and Data Recovery Circuit.” Ieee Journal of Solid-state Circuits 53 (2): 470–483.
Chicago author-date (all authors)
Verbeke, Marijn, Pieter Rombouts, Hannes Ramon, Bart Moeneclaey, Xin Yin, Johan Bauwelinck, and Guy Torfs. 2018. “A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-digital Clock and Data Recovery Circuit.” Ieee Journal of Solid-state Circuits 53 (2): 470–483.
Vancouver
1.
Verbeke M, Rombouts P, Ramon H, Moeneclaey B, Yin X, Bauwelinck J, et al. A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit. IEEE JOURNAL OF SOLID-STATE CIRCUITS. Piscataway: Ieee-inst Electrical Electronics Engineers Inc; 2018;53(2):470–83.
IEEE
[1]
M. Verbeke et al., “A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 53, no. 2, pp. 470–483, 2018.
@article{8550815,
  abstract     = {Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm(2) and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive.},
  author       = {Verbeke, Marijn and Rombouts, Pieter and Ramon, Hannes and Moeneclaey, Bart and Yin, Xin and Bauwelinck, Johan and Torfs, Guy},
  issn         = {0018-9200},
  journal      = {IEEE JOURNAL OF SOLID-STATE CIRCUITS},
  keywords     = {IBCN,BANG-BANG CLOCK,28 NM CMOS,SENSE-AMPLIFIER,FLIP-FLOP,CDR,DESIGN,JITTER,ADC,PON,All-digital clock and data recovery (AD-CDR),digital controlled,oscillator (DCO),digital loop filter (DLF),Inverse Alexander phase,detector (PD),subsampling,synthesis},
  language     = {eng},
  number       = {2},
  pages        = {470--483},
  publisher    = {Ieee-inst Electrical Electronics Engineers Inc},
  title        = {A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit},
  url          = {http://dx.doi.org/10.1109/JSSC.2017.2755690},
  volume       = {53},
  year         = {2018},
}

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