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Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Jelle Bailleul (UGent) , Lennert Jacobs (UGent) , Paolo Manfredi (UGent) , Dries Vande Ginste (UGent) and Marc Moeneclaey (UGent)
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Keywords
MMSE equalization, Chip-to-chip communication, Manufacturing tolerances, Polynomial chaos theory

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MLA
Bailleul, Jelle, et al. “Equalization of Multi-Gb/s Chip-to-Chip Interconnects Affected by Manufacturing Tolerances.” COMPUTERS & ELECTRICAL ENGINEERING, vol. 62, Elsevier BV, 2017, pp. 17–28, doi:10.1016/j.compeleceng.2017.07.020.
APA
Bailleul, J., Jacobs, L., Manfredi, P., Vande Ginste, D., & Moeneclaey, M. (2017). Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances. COMPUTERS & ELECTRICAL ENGINEERING, 62, 17–28. https://doi.org/10.1016/j.compeleceng.2017.07.020
Chicago author-date
Bailleul, Jelle, Lennert Jacobs, Paolo Manfredi, Dries Vande Ginste, and Marc Moeneclaey. 2017. “Equalization of Multi-Gb/s Chip-to-Chip Interconnects Affected by Manufacturing Tolerances.” COMPUTERS & ELECTRICAL ENGINEERING 62: 17–28. https://doi.org/10.1016/j.compeleceng.2017.07.020.
Chicago author-date (all authors)
Bailleul, Jelle, Lennert Jacobs, Paolo Manfredi, Dries Vande Ginste, and Marc Moeneclaey. 2017. “Equalization of Multi-Gb/s Chip-to-Chip Interconnects Affected by Manufacturing Tolerances.” COMPUTERS & ELECTRICAL ENGINEERING 62: 17–28. doi:10.1016/j.compeleceng.2017.07.020.
Vancouver
1.
Bailleul J, Jacobs L, Manfredi P, Vande Ginste D, Moeneclaey M. Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances. COMPUTERS & ELECTRICAL ENGINEERING. 2017;62:17–28.
IEEE
[1]
J. Bailleul, L. Jacobs, P. Manfredi, D. Vande Ginste, and M. Moeneclaey, “Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances,” COMPUTERS & ELECTRICAL ENGINEERING, vol. 62, pp. 17–28, 2017.
@article{8544348,
  author       = {{Bailleul, Jelle and Jacobs, Lennert and Manfredi, Paolo and Vande Ginste, Dries and Moeneclaey, Marc}},
  issn         = {{0045-7906}},
  journal      = {{COMPUTERS & ELECTRICAL ENGINEERING}},
  keywords     = {{MMSE equalization,Chip-to-chip communication,Manufacturing tolerances,Polynomial chaos theory}},
  language     = {{eng}},
  pages        = {{17--28}},
  publisher    = {{Elsevier BV}},
  title        = {{Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances}},
  url          = {{http://dx.doi.org/10.1016/j.compeleceng.2017.07.020}},
  volume       = {{62}},
  year         = {{2017}},
}

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