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Mind the power holes : sifting operating points in power-limited heterogeneous multicores

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Abstract
Heterogeneous chip multicore processors (HCMPs) equipped with multiple voltage-frequency (V-F) operating points provide a wide spectrum of power-performance tradeoff opportunities. This work targets the performance of HCMPs under a power cap. We show that for any performance optimization technique to work under power constraints, the default set of V-F operating points in HCMPs must be first filtered based on the application's power and performance characteristics. Attempting to find operating points of maximum performance by naively walking the default set of operating points leads the application to inefficient operating points which drain power without significant performance benefit. We call these points Power Holes (PH). Contrary to intuition, we show that even using a power-performance curve of Pareto-optimal operating points still degrades performance significantly for the same reason. We propose PH-Sifter, a fast and scalable technique that sifts the default set of operating points and eliminates power holes. We show significant performance improvement of PH-Sifter compared to Pareto sifting for three use cases: (i) maximizing performance for a single application, (ii) maximizing system throughput for multi-programmed workloads, and (iii) maximizing performance of a system in which a fraction of the power budget is reserved for a high-priority application. Our results show performance improvements of 13, 27, and 28 percent on average that reach up to 52, 91 percent, and 2.3x, respectively, for the three use cases.
Keywords
PERFORMANCE, DVFS, Heterogeneous multicores, power-limited processors, optimal operating, points, power management

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MLA
Adileh, Almutaz, et al. “Mind the Power Holes : Sifting Operating Points in Power-Limited Heterogeneous Multicores.” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 16, no. 1, 2017, pp. 56–59, doi:10.1109/LCA.2016.2616339.
APA
Adileh, A., Eyerman, S., Jaleel, A., & Eeckhout, L. (2017). Mind the power holes : sifting operating points in power-limited heterogeneous multicores. IEEE COMPUTER ARCHITECTURE LETTERS, 16(1), 56–59. https://doi.org/10.1109/LCA.2016.2616339
Chicago author-date
Adileh, Almutaz, Stijn Eyerman, Aamer Jaleel, and Lieven Eeckhout. 2017. “Mind the Power Holes : Sifting Operating Points in Power-Limited Heterogeneous Multicores.” IEEE COMPUTER ARCHITECTURE LETTERS 16 (1): 56–59. https://doi.org/10.1109/LCA.2016.2616339.
Chicago author-date (all authors)
Adileh, Almutaz, Stijn Eyerman, Aamer Jaleel, and Lieven Eeckhout. 2017. “Mind the Power Holes : Sifting Operating Points in Power-Limited Heterogeneous Multicores.” IEEE COMPUTER ARCHITECTURE LETTERS 16 (1): 56–59. doi:10.1109/LCA.2016.2616339.
Vancouver
1.
Adileh A, Eyerman S, Jaleel A, Eeckhout L. Mind the power holes : sifting operating points in power-limited heterogeneous multicores. IEEE COMPUTER ARCHITECTURE LETTERS. 2017;16(1):56–9.
IEEE
[1]
A. Adileh, S. Eyerman, A. Jaleel, and L. Eeckhout, “Mind the power holes : sifting operating points in power-limited heterogeneous multicores,” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 16, no. 1, pp. 56–59, 2017.
@article{8542498,
  abstract     = {Heterogeneous chip multicore processors (HCMPs) equipped with multiple voltage-frequency (V-F) operating points provide a wide spectrum of power-performance tradeoff opportunities. This work targets the performance of HCMPs under a power cap. We show that for any performance optimization technique to work under power constraints, the default set of V-F operating points in HCMPs must be first filtered based on the application's power and performance characteristics. Attempting to find operating points of maximum performance by naively walking the default set of operating points leads the application to inefficient operating points which drain power without significant performance benefit. We call these points Power Holes (PH). Contrary to intuition, we show that even using a power-performance curve of Pareto-optimal operating points still degrades performance significantly for the same reason. We propose PH-Sifter, a fast and scalable technique that sifts the default set of operating points and eliminates power holes. We show significant performance improvement of PH-Sifter compared to Pareto sifting for three use cases: (i) maximizing performance for a single application, (ii) maximizing system throughput for multi-programmed workloads, and (iii) maximizing performance of a system in which a fraction of the power budget is reserved for a high-priority application. Our results show performance improvements of 13, 27, and 28 percent on average that reach up to 52, 91 percent, and 2.3x, respectively, for the three use cases.},
  author       = {Adileh, Almutaz and Eyerman, Stijn and Jaleel, Aamer and Eeckhout, Lieven},
  issn         = {1556-6056},
  journal      = {IEEE COMPUTER ARCHITECTURE LETTERS},
  keywords     = {PERFORMANCE,DVFS,Heterogeneous multicores,power-limited processors,optimal operating,points,power management},
  language     = {eng},
  number       = {1},
  pages        = {56--59},
  title        = {Mind the power holes : sifting operating points in power-limited heterogeneous multicores},
  url          = {http://dx.doi.org/10.1109/LCA.2016.2616339},
  volume       = {16},
  year         = {2017},
}

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