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Shared resource aware scheduling on power-constrained tiled many-core processors

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Abstract
Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today's power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases exponentially. This calls for hierarchical solutions, such as on-chip voltage regulators per-tile rather than per-core, along with multi-level power management. As power-driven adaptation of shared resources affects multiple threads at once, the efficiency in a tile-organized many-core processor architecture hinges on the ability to co-schedule compatible threads to tiles in tandem with hardware adaptations per tile and per core. In this paper, we propose a two-tier hierarchical power management methodology to exploit per tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior. On a 256-core setup with 4 cores per tile, we show that adding sensitivity-based thread migration to a two-tier power manager improves system performance by 10% on average (and up to 20%) while using 4x less on-chip voltage regulators. It also achieves a performance advantage of 4.2% on average (and up to 12%) over existing solutions that do not take DVFS sensitivity into account. (C) 2016 Elsevier Inc. All rights reserved.
Keywords
CHIP MULTIPROCESSORS, PERFORMANCE, MANAGEMENT, SYSTEMS, CACHE, Many-core tiled architecture, Thread migration, Power budget, Adaptive, microarchitecture

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Chicago
Jha, Sudhanshu Shekhar, Wim Heirman, Ayose Falcon, Jordi Tubella, Antonio Gonzalez, and Lieven Eeckhout. 2017. “Shared Resource Aware Scheduling on Power-constrained Tiled Many-core Processors.” Journal of Parallel and Distributed Computing 100: 30–41.
APA
Jha, S. S., Heirman, W., Falcon, A., Tubella, J., Gonzalez, A., & Eeckhout, L. (2017). Shared resource aware scheduling on power-constrained tiled many-core processors. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 100, 30–41.
Vancouver
1.
Jha SS, Heirman W, Falcon A, Tubella J, Gonzalez A, Eeckhout L. Shared resource aware scheduling on power-constrained tiled many-core processors. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING. San diego: Academic Press Inc Elsevier Science; 2017;100:30–41.
MLA
Jha, Sudhanshu Shekhar et al. “Shared Resource Aware Scheduling on Power-constrained Tiled Many-core Processors.” JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 100 (2017): 30–41. Print.
@article{8542496,
  abstract     = {Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today's power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases exponentially. This calls for hierarchical solutions, such as on-chip voltage regulators per-tile rather than per-core, along with multi-level power management. As power-driven adaptation of shared resources affects multiple threads at once, the efficiency in a tile-organized many-core processor architecture hinges on the ability to co-schedule compatible threads to tiles in tandem with hardware adaptations per tile and per core. In this paper, we propose a two-tier hierarchical power management methodology to exploit per tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior. On a 256-core setup with 4 cores per tile, we show that adding sensitivity-based thread migration to a two-tier power manager improves system performance by 10% on average (and up to 20%) while using 4x less on-chip voltage regulators. It also achieves a performance advantage of 4.2% on average (and up to 12%) over existing solutions that do not take DVFS sensitivity into account. (C) 2016 Elsevier Inc. All rights reserved.},
  author       = {Jha, Sudhanshu Shekhar and Heirman, Wim and Falcon, Ayose and Tubella, Jordi and Gonzalez, Antonio and Eeckhout, Lieven},
  issn         = {0743-7315},
  journal      = {JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING},
  keywords     = {CHIP MULTIPROCESSORS,PERFORMANCE,MANAGEMENT,SYSTEMS,CACHE,Many-core tiled architecture,Thread migration,Power budget,Adaptive,microarchitecture},
  language     = {eng},
  pages        = {30--41},
  publisher    = {Academic Press Inc Elsevier Science},
  title        = {Shared resource aware scheduling on power-constrained tiled many-core processors},
  url          = {http://dx.doi.org/10.1016/j.jpdc.2016.10.001},
  volume       = {100},
  year         = {2017},
}

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