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A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration

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EXTRA (Exploiting eXascale Technology with Reconfigurable Architectures)
Abstract
Run-time reconfiguration in FPGAs is an important feature that offers design flexibility under low-cost silicon area and power budgets, at the cost of reconfiguration overhead. The reconfiguration time overhead produced by the conventional configuration ports (such as ICAP) is too high for the reconfiguration technology to be embraced as a standard. Furthermore, the current FPGA configuration memory architecture restricts the access of configuration data to the frame level; this significantly delays the reconfiguration process. The work presented in this paper explores the design space of the configuration memory architecture that fits the design of large FPGAs and is suitable to accomplish needs for ultra-fast reconfiguration. Therefore, the proposed method could be a stepping stone for next generation FPGA configuration memory architecture. Our simulation results show a reconfiguration speed gain of a factor of at least 1000 for substantially big parameterized applications that come with the cost of extra auxiliary hardware used on top of the column-based FPGA architecture.
Keywords
FPGA, Reconfiguration, Dynamic Circuit Specialization (DCS), Polymorphic Register File (PRF) memory, Network-on- Chip (NoC)

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Chicago
Kulkarni, Amit, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, and Ana Lucia Varbanescu. 2017. “A NoC-based Custom FPGA Configuration Memory Architecture for Ultra-fast Micro-reconfiguration.” In 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) , 203–206. IEEE .
APA
Kulkarni, A., Bahrebar, P., Stroobandt, D., Stramondo, G., Bogdan Ciobanu, C., & Varbanescu, A. L. (2017). A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration. 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) (pp. 203–206). Presented at the 16th IEEE International Conference on Field-Programmable Technology (ICFPT) , IEEE .
Vancouver
1.
Kulkarni A, Bahrebar P, Stroobandt D, Stramondo G, Bogdan Ciobanu C, Varbanescu AL. A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration. 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) . IEEE ; 2017. p. 203–6.
MLA
Kulkarni, Amit, Poona Bahrebar, Dirk Stroobandt, et al. “A NoC-based Custom FPGA Configuration Memory Architecture for Ultra-fast Micro-reconfiguration.” 2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) . IEEE , 2017. 203–206. Print.
@inproceedings{8535608,
  abstract     = {Run-time reconfiguration in FPGAs is an important feature that offers design flexibility under low-cost silicon area and  power budgets, at the cost of reconfiguration overhead. The reconfiguration time overhead produced by the conventional configuration ports (such as ICAP) is too high for the reconfiguration technology to be embraced as a standard. Furthermore, the current FPGA configuration memory architecture restricts the access of configuration data to the frame level; this significantly delays the reconfiguration process. The work presented in this paper explores the design space of the configuration memory architecture that fits the design of large FPGAs and is suitable to accomplish needs for ultra-fast reconfiguration. Therefore, the proposed method could be a stepping stone for next generation FPGA configuration memory architecture. Our simulation results show a reconfiguration speed gain of a factor of at least 1000 for substantially big parameterized applications that come with the cost of extra auxiliary hardware used on top of  the column-based FPGA architecture.},
  author       = {Kulkarni, Amit and Bahrebar, Poona and Stroobandt, Dirk and Stramondo, Giulio and Bogdan Ciobanu, Catalin  and Varbanescu, Ana Lucia},
  booktitle    = {2017 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY (ICFPT) },
  isbn         = {978-1-5386-2656-6},
  keyword      = {FPGA,Reconfiguration,Dynamic Circuit Specialization (DCS),Polymorphic Register File (PRF) memory,Network-on- Chip (NoC)},
  language     = {eng},
  location     = {Melbourne, Australia},
  pages        = {203--206},
  publisher    = {IEEE },
  title        = {A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration},
  year         = {2017},
}

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