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Dynamically reconfigurable architecture for fault-tolerant 2D Networks-on-Chip

Poona Bahrebar (UGent) , Azarakhsh Jalalvand (UGent) and Dirk Stroobandt (UGent)
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Abstract
With the increasing device scaling in the semiconductor technology, the necessity for designing robust and efficient Networks-on-Chip (NoCs) is more pronounced. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. In this paper, a dynamically reconfigurable technique is proposed to target fault-tolerance and minimal routing in a unified manner. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.
Keywords
Network-on-Chip (NoC), fault-tolerant routing methods, minimal paths, reconfiguration, deadlock

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Please use this url to cite or link to this publication:

Chicago
Bahrebar, Poona, Azarakhsh Jalalvand, and Dirk Stroobandt. 2017. “Dynamically Reconfigurable Architecture for Fault-tolerant 2D Networks-on-Chip.” In Proceedings of the 26th International Conference on Computer Communication and Networks (ICCCN), 1–7. IEEE.
APA
Bahrebar, P., Jalalvand, A., & Stroobandt, D. (2017). Dynamically reconfigurable architecture for fault-tolerant 2D Networks-on-Chip. Proceedings of the 26th International Conference on Computer Communication and Networks (ICCCN) (pp. 1–7). Presented at the International Conference on Computer Communication and Networks (ICCCN), IEEE.
Vancouver
1.
Bahrebar P, Jalalvand A, Stroobandt D. Dynamically reconfigurable architecture for fault-tolerant 2D Networks-on-Chip. Proceedings of the 26th International Conference on Computer Communication and Networks (ICCCN). IEEE; 2017. p. 1–7.
MLA
Bahrebar, Poona, Azarakhsh Jalalvand, and Dirk Stroobandt. “Dynamically Reconfigurable Architecture for Fault-tolerant 2D Networks-on-Chip.” Proceedings of the 26th International Conference on Computer Communication and Networks (ICCCN). IEEE, 2017. 1–7. Print.
@inproceedings{8533125,
  abstract     = {With the increasing device scaling in the semiconductor technology, the necessity for designing robust and efficient Networks-on-Chip (NoCs) is more pronounced. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. In this paper, a dynamically reconfigurable technique is proposed to target fault-tolerance and minimal routing in a unified manner. To accomplish this goal, the router architecture is modified to enable the frequently  communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.},
  author       = {Bahrebar, Poona and Jalalvand, Azarakhsh and Stroobandt, Dirk},
  booktitle    = {Proceedings of the 26th International Conference on Computer Communication and Networks (ICCCN)},
  isbn         = {9781509029914},
  keyword      = {Network-on-Chip (NoC),fault-tolerant routing methods,minimal paths,reconfiguration,deadlock},
  language     = {eng},
  location     = {Vancouver, BC, Canada},
  pages        = {1--7},
  publisher    = {IEEE},
  title        = {Dynamically reconfigurable architecture for fault-tolerant 2D Networks-on-Chip},
  url          = {http://dx.doi.org/10.1109/icccn.2017.8038407},
  year         = {2017},
}

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