Modeling superscalar processor memory-level parallelism
- Author
- Sam Van den Steen (UGent) and Lieven Eeckhout (UGent)
- Organization
- Abstract
- This paper proposes an analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload's inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9 percent for previous work to 3.6 percent on average for the proposed model.
- Keywords
- Micro-architecture, Analytical model, Memory Level Parallelism, Modeling, memory level parallelism (MLP), micro-architecture
Downloads
-
CAL 2016.pdf
- full text (Accepted manuscript)
- |
- open access
- |
- |
- 226.11 KB
-
(...).pdf
- full text (Published version)
- |
- UGent only
- |
- |
- 331.91 KB
Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-8531525
- MLA
- Van den Steen, Sam, and Lieven Eeckhout. “Modeling Superscalar Processor Memory-Level Parallelism.” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 17, no. 1, 2018, pp. 9–12, doi:10.1109/lca.2017.2701370.
- APA
- Van den Steen, S., & Eeckhout, L. (2018). Modeling superscalar processor memory-level parallelism. IEEE COMPUTER ARCHITECTURE LETTERS, 17(1), 9–12. https://doi.org/10.1109/lca.2017.2701370
- Chicago author-date
- Van den Steen, Sam, and Lieven Eeckhout. 2018. “Modeling Superscalar Processor Memory-Level Parallelism.” IEEE COMPUTER ARCHITECTURE LETTERS 17 (1): 9–12. https://doi.org/10.1109/lca.2017.2701370.
- Chicago author-date (all authors)
- Van den Steen, Sam, and Lieven Eeckhout. 2018. “Modeling Superscalar Processor Memory-Level Parallelism.” IEEE COMPUTER ARCHITECTURE LETTERS 17 (1): 9–12. doi:10.1109/lca.2017.2701370.
- Vancouver
- 1.Van den Steen S, Eeckhout L. Modeling superscalar processor memory-level parallelism. IEEE COMPUTER ARCHITECTURE LETTERS. 2018;17(1):9–12.
- IEEE
- [1]S. Van den Steen and L. Eeckhout, “Modeling superscalar processor memory-level parallelism,” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 17, no. 1, pp. 9–12, 2018.
@article{8531525,
abstract = {This paper proposes an analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload's inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9 percent for previous work to 3.6 percent on average for the proposed model.},
author = {Van den Steen, Sam and Eeckhout, Lieven},
issn = {1556-6056},
journal = {IEEE COMPUTER ARCHITECTURE LETTERS},
keywords = {Micro-architecture,Analytical model,Memory Level Parallelism,Modeling,memory level parallelism (MLP),micro-architecture},
language = {eng},
number = {1},
pages = {9--12},
title = {Modeling superscalar processor memory-level parallelism},
url = {http://dx.doi.org/10.1109/lca.2017.2701370},
volume = {17},
year = {2018},
}
- Altmetric
- View in Altmetric
- Web of Science
- Times cited: