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Modeling superscalar processor memory-level parallelism

Sam Van den Steen (UGent) and Lieven Eeckhout (UGent)
(2018) IEEE COMPUTER ARCHITECTURE LETTERS . 17(1). p.9-12
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Abstract
This paper proposes a analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload’s inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9% for previous work to 3.6% on average for the proposed model.
Keywords
Micro-architecture, Analytical model, Memory Level Parallelism

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Citation

Please use this url to cite or link to this publication:

Chicago
Van den Steen, Sam, and Lieven Eeckhout. 2018. “Modeling Superscalar Processor Memory-level Parallelism.” Ieee Computer Architecture Letters 17 (1): 9–12.
APA
Van den Steen, S., & Eeckhout, L. (2018). Modeling superscalar processor memory-level parallelism. IEEE COMPUTER ARCHITECTURE LETTERS , 17(1), 9–12.
Vancouver
1.
Van den Steen S, Eeckhout L. Modeling superscalar processor memory-level parallelism. IEEE COMPUTER ARCHITECTURE LETTERS . IEEE; 2018;17(1):9–12.
MLA
Van den Steen, Sam, and Lieven Eeckhout. “Modeling Superscalar Processor Memory-level Parallelism.” IEEE COMPUTER ARCHITECTURE LETTERS 17.1 (2018): 9–12. Print.
@article{8531525,
  abstract     = {This paper proposes a analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload’s inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9% for previous work to 3.6% on average for the proposed model.},
  author       = {Van den Steen, Sam and Eeckhout, Lieven},
  issn         = {1556-6056},
  journal      = {IEEE COMPUTER ARCHITECTURE LETTERS },
  keywords     = {Micro-architecture,Analytical model,Memory Level Parallelism},
  language     = {eng},
  number       = {1},
  pages        = {9--12},
  publisher    = {IEEE},
  title        = {Modeling superscalar processor memory-level parallelism},
  url          = {http://dx.doi.org/10.1109/lca.2017.2701370},
  volume       = {17},
  year         = {2018},
}
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