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Pixie : a heterogeneous virtual coarse-grained reconfigurable array for high performance image processing applications

Author
Organization
Project
EXTRA (Exploiting eXascale Technology with Reconfigurable Architectures)
Abstract
Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications. The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The CGRAs are ASICs and therefore, expensive to produce. However, Field Programmable Gate Arrays (FPGAs) are relatively cheaper for low volume products but they are not so easily programmable. We combine best of both worlds by implementing a Virtual Coarse-Grained Reconfigurable Array (VCGRA) on FPGA. VCGRAs are a trade off between FPGA with large routing overheads and ASICs. In this perspective, we present a novel heterogeneous Virtual Coarse-Grained Reconfigurable Array (VCGRA) called "Pixie'" which is suitable for implementing high-performance image processing applications. The proposed VCGRA contains generic processing elements and virtual channels that are described using the Hardware Description Language VHDL. Both elements have been optimized by using the parameterized configuration tool flow and result in a resource reduction of 24% for each processing elements and 82% for each virtual channels respectively.
Keywords
FPGA, CGRA, Reconfiguration, TLUT, TCON

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Citation

Please use this url to cite or link to this publication:

Chicago
Kulkarni, Amit, Dirk Stroobandt, Andre Werner, Florian Fricke, and Michael Huebner. 2017. “Pixie : a Heterogeneous Virtual Coarse-grained Reconfigurable Array for High Performance Image Processing Applications.” In 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), 1–6. Monterey, CA, USA: arxiv.org.
APA
Kulkarni, A., Stroobandt, D., Werner, A., Fricke, F., & Huebner, M. (2017). Pixie : a heterogeneous virtual coarse-grained reconfigurable array for high performance image processing applications. 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017) (pp. 1–6). Presented at the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), Monterey, CA, USA: arxiv.org.
Vancouver
1.
Kulkarni A, Stroobandt D, Werner A, Fricke F, Huebner M. Pixie : a heterogeneous virtual coarse-grained reconfigurable array for high performance image processing applications. 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017). Monterey, CA, USA: arxiv.org; 2017. p. 1–6.
MLA
Kulkarni, Amit, Dirk Stroobandt, Andre Werner, et al. “Pixie : a Heterogeneous Virtual Coarse-grained Reconfigurable Array for High Performance Image Processing Applications.” 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017). Monterey, CA, USA: arxiv.org, 2017. 1–6. Print.
@inproceedings{8519618,
  abstract     = {Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications.  The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The CGRAs are ASICs and therefore, expensive to produce. However, Field Programmable Gate Arrays (FPGAs) are relatively cheaper for low volume products but they are not so easily programmable. We combine best of both worlds by implementing a Virtual Coarse-Grained Reconfigurable Array (VCGRA) on FPGA. VCGRAs are a trade off between FPGA with large routing overheads and ASICs. In this perspective, we present a novel heterogeneous Virtual Coarse-Grained Reconfigurable Array (VCGRA) called {\textacutedbl}Pixie'{\textacutedbl} which is suitable for implementing high-performance image processing applications. 
The proposed VCGRA contains generic processing elements and virtual channels that are described using the Hardware Description Language VHDL. Both elements have been optimized by using the parameterized configuration tool flow and result in a resource reduction of 24\% for each processing elements and 82\% for each virtual channels respectively. 
},
  articleno    = {OLAF/2017/01},
  author       = {Kulkarni, Amit and Stroobandt, Dirk and Werner, Andre and Fricke, Florian and Huebner, Michael},
  booktitle    = {3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017)},
  keyword      = {FPGA,CGRA,Reconfiguration,TLUT,TCON},
  language     = {eng},
  location     = {Monterey, CA, USA},
  pages        = {OLAF/2017/01:1--OLAF/2017/01:6},
  publisher    = {arxiv.org},
  title        = {Pixie : a heterogeneous virtual coarse-grained reconfigurable array for high performance image processing applications},
  url          = {https://arxiv.org/abs/1705.01738v1},
  year         = {2017},
}