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A bimodal scheduler for coarse-grained reconfigurable arrays

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Abstract
Compilers for Course-Grained Reconfigurable Array (CGRA) architectures suffer from long compilation times and code quality levels far below the theoretical upper bounds. This article presents a new scheduler, called the Bimodal Modulo Scheduler (BMS), to map inner loops onto (heterogeneous) CGRAs of the Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) family. BMS significantly outperforms existing schedulers for similar architectures in terms of generated code quality and compilation time. This is achieved by combining new schemes for backtracking with extended and adapted forms of priority functions and cost functions, as described in the article. BMS is evaluated by mapping multimedia and software-defined radio benchmarks onto tuned ADRES instances.
Keywords
Architecture, Compiler, Performance, Modulo scheduling, placement and, routing, cost functions

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Citation

Please use this url to cite or link to this publication:

MLA
Theocharis, Panagiotis, and Bjorn De Sutter. “A Bimodal Scheduler for Coarse-grained Reconfigurable Arrays.” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 13.2 (2016): n. pag. Print.
APA
Theocharis, P., & De Sutter, B. (2016). A bimodal scheduler for coarse-grained reconfigurable arrays. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 13(2).
Chicago author-date
Theocharis, Panagiotis, and Bjorn De Sutter. 2016. “A Bimodal Scheduler for Coarse-grained Reconfigurable Arrays.” Acm Transactions on Architecture and Code Optimization 13 (2).
Chicago author-date (all authors)
Theocharis, Panagiotis, and Bjorn De Sutter. 2016. “A Bimodal Scheduler for Coarse-grained Reconfigurable Arrays.” Acm Transactions on Architecture and Code Optimization 13 (2).
Vancouver
1.
Theocharis P, De Sutter B. A bimodal scheduler for coarse-grained reconfigurable arrays. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. New york: Assoc Computing Machinery; 2016;13(2).
IEEE
[1]
P. Theocharis and B. De Sutter, “A bimodal scheduler for coarse-grained reconfigurable arrays,” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, vol. 13, no. 2, 2016.
@article{8501982,
  abstract     = {Compilers for Course-Grained Reconfigurable Array (CGRA) architectures suffer from long compilation times and code quality levels far below the theoretical upper bounds. This article presents a new scheduler, called the Bimodal Modulo Scheduler (BMS), to map inner loops onto (heterogeneous) CGRAs of the Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) family. BMS significantly outperforms existing schedulers for similar architectures in terms of generated code quality and compilation time. This is achieved by combining new schemes for backtracking with extended and adapted forms of priority functions and cost functions, as described in the article. BMS is evaluated by mapping multimedia and software-defined radio benchmarks onto tuned ADRES instances.},
  articleno    = {15},
  author       = {Theocharis, Panagiotis and De Sutter, Bjorn},
  issn         = {1544-3566},
  journal      = {ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION},
  keywords     = {Architecture,Compiler,Performance,Modulo scheduling,placement and,routing,cost functions},
  language     = {eng},
  number       = {2},
  pages        = {26},
  publisher    = {Assoc Computing Machinery},
  title        = {A bimodal scheduler for coarse-grained reconfigurable arrays},
  url          = {http://dx.doi.org/10.1145/2893475},
  volume       = {13},
  year         = {2016},
}

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