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  • EXTRA
Abstract
To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. %The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.
Keywords
reconfigurable platform, EXTRA

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Citation

Please use this url to cite or link to this publication:

MLA
Stroobandt, Dirk et al. “EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures.” Design Automation and Test in Europe. IEEE, 1996. Print.
APA
Stroobandt, D., Varbanescu, A. L., Ciobanu, C. B., Al Kadi, M., Brokalakis, A., Charitopoulos, G., Todman, T., et al. (1996). EXTRA: towards the exploitation of eXascale technology for reconfigurable architectures. Design Automation and Test in Europe. Presented at the Design Automation and Test in Europe, IEEE.
Chicago author-date
Stroobandt, Dirk, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, et al. 1996. “EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures.” In Design Automation and Test in Europe. IEEE.
Chicago author-date (all authors)
Stroobandt, Dirk, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios Pnevmatikatos, Elias Vansteenkiste, Wayne Luk, Marco D Santambrogio, Donatella Sciuto, Michael Huebner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakisy, and Alex JW Thom. 1996. “EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures.” In Design Automation and Test in Europe. IEEE.
Vancouver
1.
Stroobandt D, Varbanescu AL, Ciobanu CB, Al Kadi M, Brokalakis A, Charitopoulos G, et al. EXTRA: towards the exploitation of eXascale technology for reconfigurable architectures. Design Automation and Test in Europe. IEEE; 1996.
IEEE
[1]
D. Stroobandt et al., “EXTRA: towards the exploitation of eXascale technology for reconfigurable architectures,” in Design Automation and Test in Europe, Dresden, GERMANY, 1996.
@inproceedings{8115230,
  abstract     = {To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on.
%The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future.
EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.},
  author       = {Stroobandt, Dirk and Varbanescu, Ana Lucia and Ciobanu, Catalin Bogdan and Al Kadi, Muhammed and Brokalakis, Andreas and Charitopoulos, George and Todman, Tim and Niu, Xinyu and Pnevmatikatos, Dionisios and Vansteenkiste, Elias and Luk, Wayne and Santambrogio, Marco D and Sciuto, Donatella and Huebner, Michael and Becker, Tobias and Gaydadjiev, Georgi and Nikitakisy, Antonis and Thom, Alex JW},
  booktitle    = {Design Automation and Test in Europe},
  keywords     = {reconfigurable platform,EXTRA},
  language     = {eng},
  location     = {Dresden, GERMANY},
  pages        = {6},
  publisher    = {IEEE},
  title        = {EXTRA: towards the exploitation of eXascale technology for reconfigurable architectures},
  year         = {1996},
}