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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Brahim Al Farisi (UGent) , Karel Heyse (UGent) , Karel Bruneel (UGent) , João Cardoso and Dirk Stroobandt (UGent)
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Abstract
Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %.
Keywords
Routing, SYSTEMS, Dynamic partial reconfiguration, FPGA

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Chicago
Al Farisi, Brahim, Karel Heyse, Karel Bruneel, João Cardoso, and Dirk Stroobandt. 2015. “Enabling FPGA Routing Configuration Sharing in Dynamic Partial Reconfiguration.” Design Automation for Embedded Systems 19 (1-2): 189–221.
APA
Al Farisi, B., Heyse, K., Bruneel, K., Cardoso, J., & Stroobandt, D. (2015). Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 19(1-2), 189–221.
Vancouver
1.
Al Farisi B, Heyse K, Bruneel K, Cardoso J, Stroobandt D. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS. 2015;19(1-2):189–221.
MLA
Al Farisi, Brahim, Karel Heyse, Karel Bruneel, et al. “Enabling FPGA Routing Configuration Sharing in Dynamic Partial Reconfiguration.” DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 19.1-2 (2015): 189–221. Print.
@article{8102379,
  abstract     = {Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 \% of the routing configuration static and therefore reduce the routing reconfiguration time by 50 \%, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 \%.},
  author       = {Al Farisi, Brahim and Heyse, Karel and Bruneel, Karel and Cardoso, Jo{\~a}o and Stroobandt, Dirk},
  issn         = {0929-5585},
  journal      = {DESIGN AUTOMATION FOR EMBEDDED SYSTEMS},
  language     = {eng},
  number       = {1-2},
  pages        = {189--221},
  title        = {Enabling FPGA routing configuration sharing in dynamic partial reconfiguration},
  url          = {http://dx.doi.org/10.1007/s10617-014-9143-8},
  volume       = {19},
  year         = {2015},
}

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