
Performance optimization of au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate
- Author
- J Hu, S Stoffels, S Lenci, Benoit Bakeroot (UGent) , B De Jaeger, M Van Hove, N Ronchi, R Venegas, H Liang, M Zhao, G Groeseneken and S Decoutere
- Organization
- Abstract
- In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver similar to 4 A at 2 V and show a median leakage of 1.3 mu A at 25 degrees C and 3.8 mu A at 150 degrees C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of similar to 600 V for the GET-SBDs with LAC larger than 5 mu m. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 mu m-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 mu m) and remains at a value of similar to 10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.
- Keywords
- POWER DIODE, TiN, Schottky barrier diode (SBD), leakage reduction, VOLTAGE, ORIENTATION, TRANSISTORS, ORIGIN, 200-mm substrate, AlGaN/GaN, WORK FUNCTION, Au-free, HYBRID ANODE, edge termination
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Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-8032153
- MLA
- Hu, J., et al. “Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode with Gated Edge Termination on 200-Mm Silicon Substrate.” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, no. 3, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2016, pp. 997–1004, doi:10.1109/TED.2016.2515566.
- APA
- Hu, J., Stoffels, S., Lenci, S., Bakeroot, B., De Jaeger, B., Van Hove, M., … Decoutere, S. (2016). Performance optimization of au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate. IEEE TRANSACTIONS ON ELECTRON DEVICES, 63(3), 997–1004. https://doi.org/10.1109/TED.2016.2515566
- Chicago author-date
- Hu, J, S Stoffels, S Lenci, Benoit Bakeroot, B De Jaeger, M Van Hove, N Ronchi, et al. 2016. “Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode with Gated Edge Termination on 200-Mm Silicon Substrate.” IEEE TRANSACTIONS ON ELECTRON DEVICES 63 (3): 997–1004. https://doi.org/10.1109/TED.2016.2515566.
- Chicago author-date (all authors)
- Hu, J, S Stoffels, S Lenci, Benoit Bakeroot, B De Jaeger, M Van Hove, N Ronchi, R Venegas, H Liang, M Zhao, G Groeseneken, and S Decoutere. 2016. “Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode with Gated Edge Termination on 200-Mm Silicon Substrate.” IEEE TRANSACTIONS ON ELECTRON DEVICES 63 (3): 997–1004. doi:10.1109/TED.2016.2515566.
- Vancouver
- 1.Hu J, Stoffels S, Lenci S, Bakeroot B, De Jaeger B, Van Hove M, et al. Performance optimization of au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2016;63(3):997–1004.
- IEEE
- [1]J. Hu et al., “Performance optimization of au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate,” IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 63, no. 3, pp. 997–1004, 2016.
@article{8032153, abstract = {{In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver similar to 4 A at 2 V and show a median leakage of 1.3 mu A at 25 degrees C and 3.8 mu A at 150 degrees C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of similar to 600 V for the GET-SBDs with LAC larger than 5 mu m. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 mu m-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 mu m) and remains at a value of similar to 10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.}}, author = {{Hu, J and Stoffels, S and Lenci, S and Bakeroot, Benoit and De Jaeger, B and Van Hove, M and Ronchi, N and Venegas, R and Liang, H and Zhao, M and Groeseneken, G and Decoutere, S}}, issn = {{0018-9383}}, journal = {{IEEE TRANSACTIONS ON ELECTRON DEVICES}}, keywords = {{POWER DIODE,TiN,Schottky barrier diode (SBD),leakage reduction,VOLTAGE,ORIENTATION,TRANSISTORS,ORIGIN,200-mm substrate,AlGaN/GaN,WORK FUNCTION,Au-free,HYBRID ANODE,edge termination}}, language = {{eng}}, number = {{3}}, pages = {{997--1004}}, publisher = {{IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC}}, title = {{Performance optimization of au-free lateral AlGaN/GaN Schottky barrier diode with gated edge termination on 200-mm silicon substrate}}, url = {{http://doi.org/10.1109/TED.2016.2515566}}, volume = {{63}}, year = {{2016}}, }
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