
Nyquist-criterion based design of a CT Sigma Delta-ADC with a reduced number of comparators
- Author
- Jeroen De Maeyer (UGent) , Pieter Rombouts (UGent) and Ludo Weyten (UGent)
- Organization
- Abstract
- In this paper we present a prototype continuous time Sigma Delta-modulator in a 0.35 mu m technology. The circuit has a 6-bit internal quantizer. Through the combination of a modified architecture and comparator interpolation this high quantizer resolution is achieved with only 15 comparators. However, it turns out that this approach imposes a severe speed constraint on the analog adder circuit. The modulator consists of a third-order loop and special care was taken in the design of the loop filter. The presented design has two particular features. First, an explicit and controlled delay of 0.25 times the sampling period is introduced in the loop. Second, the Nyquist stability criterion and the vector gain margin are adopted to design a robustly stable modulator loop filter. This way our modulator does not require any tuning or trimming of the filter coefficients. Measurement results show a peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.
- Keywords
- Continuous time Sigma Delta modulation, Analog-to-digital conversion, DYNAMIC-RANGE, CLOCK JITTER, SIGNAL BANDWIDTH, A/D CONVERSION, MODULATORS, CONVERTER, RECEIVERS, FEEDBACK
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-770946
- MLA
- De Maeyer, Jeroen, et al. “Nyquist-Criterion Based Design of a CT Sigma Delta-ADC with a Reduced Number of Comparators.” INTEGRATION-THE VLSI JOURNAL, vol. 42, no. 1, 2009, pp. 61–67, doi:10.1016/j.vlsi.2008.06.003.
- APA
- De Maeyer, J., Rombouts, P., & Weyten, L. (2009). Nyquist-criterion based design of a CT Sigma Delta-ADC with a reduced number of comparators. INTEGRATION-THE VLSI JOURNAL, 42(1), 61–67. https://doi.org/10.1016/j.vlsi.2008.06.003
- Chicago author-date
- De Maeyer, Jeroen, Pieter Rombouts, and Ludo Weyten. 2009. “Nyquist-Criterion Based Design of a CT Sigma Delta-ADC with a Reduced Number of Comparators.” INTEGRATION-THE VLSI JOURNAL 42 (1): 61–67. https://doi.org/10.1016/j.vlsi.2008.06.003.
- Chicago author-date (all authors)
- De Maeyer, Jeroen, Pieter Rombouts, and Ludo Weyten. 2009. “Nyquist-Criterion Based Design of a CT Sigma Delta-ADC with a Reduced Number of Comparators.” INTEGRATION-THE VLSI JOURNAL 42 (1): 61–67. doi:10.1016/j.vlsi.2008.06.003.
- Vancouver
- 1.De Maeyer J, Rombouts P, Weyten L. Nyquist-criterion based design of a CT Sigma Delta-ADC with a reduced number of comparators. INTEGRATION-THE VLSI JOURNAL. 2009;42(1):61–7.
- IEEE
- [1]J. De Maeyer, P. Rombouts, and L. Weyten, “Nyquist-criterion based design of a CT Sigma Delta-ADC with a reduced number of comparators,” INTEGRATION-THE VLSI JOURNAL, vol. 42, no. 1, pp. 61–67, 2009.
@article{770946, abstract = {{In this paper we present a prototype continuous time Sigma Delta-modulator in a 0.35 mu m technology. The circuit has a 6-bit internal quantizer. Through the combination of a modified architecture and comparator interpolation this high quantizer resolution is achieved with only 15 comparators. However, it turns out that this approach imposes a severe speed constraint on the analog adder circuit. The modulator consists of a third-order loop and special care was taken in the design of the loop filter. The presented design has two particular features. First, an explicit and controlled delay of 0.25 times the sampling period is introduced in the loop. Second, the Nyquist stability criterion and the vector gain margin are adopted to design a robustly stable modulator loop filter. This way our modulator does not require any tuning or trimming of the filter coefficients. Measurement results show a peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.}}, author = {{De Maeyer, Jeroen and Rombouts, Pieter and Weyten, Ludo}}, issn = {{0167-9260}}, journal = {{INTEGRATION-THE VLSI JOURNAL}}, keywords = {{Continuous time Sigma Delta modulation,Analog-to-digital conversion,DYNAMIC-RANGE,CLOCK JITTER,SIGNAL BANDWIDTH,A/D CONVERSION,MODULATORS,CONVERTER,RECEIVERS,FEEDBACK}}, language = {{eng}}, number = {{1}}, pages = {{61--67}}, title = {{Nyquist-criterion based design of a CT Sigma Delta-ADC with a reduced number of comparators}}, url = {{http://doi.org/10.1016/j.vlsi.2008.06.003}}, volume = {{42}}, year = {{2009}}, }
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