Architectural study of reconfigurable photonic networks-on-chip for multi-core processors
- Author
- Christof Debaes, Iñigo Artundo, Wim Heirman (UGent) , Mikel Loperena, Jan Van Campenhout (UGent) and Hugo Thienpont
- Organization
- Abstract
- Photonic Networks-on-Chip (NoCs) have become a promising route to interconnect processor cores on chip multiprocessors (CMP) in a power efficient way. Although several photonic NoC proposals exist, their use is limited to the communication of large data messages due to a relatively long set-up time for the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically to the evolving traffic situation. This way, long photonic channel set-up times can be tolerated which makes our approach more compatible in the context of shared-memory CMPs.
- Keywords
- Photonic switching systems, Parallel architectures, Reconfigurable architectures, Optical interconnections, Multiprocessor interconnection, Optical communication
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-767773
- MLA
- Debaes, Christof, et al. “Architectural Study of Reconfigurable Photonic Networks-on-Chip for Multi-Core Processors.” Annual Meeting of the IEEE Photonics Society, 22nd, Proceedings, IEEE, 2009, pp. 266–67.
- APA
- Debaes, C., Artundo, I., Heirman, W., Loperena, M., Van Campenhout, J., & Thienpont, H. (2009). Architectural study of reconfigurable photonic networks-on-chip for multi-core processors. Annual Meeting of the IEEE Photonics Society, 22nd, Proceedings, 266–267. IEEE.
- Chicago author-date
- Debaes, Christof, Iñigo Artundo, Wim Heirman, Mikel Loperena, Jan Van Campenhout, and Hugo Thienpont. 2009. “Architectural Study of Reconfigurable Photonic Networks-on-Chip for Multi-Core Processors.” In Annual Meeting of the IEEE Photonics Society, 22nd, Proceedings, 266–67. IEEE.
- Chicago author-date (all authors)
- Debaes, Christof, Iñigo Artundo, Wim Heirman, Mikel Loperena, Jan Van Campenhout, and Hugo Thienpont. 2009. “Architectural Study of Reconfigurable Photonic Networks-on-Chip for Multi-Core Processors.” In Annual Meeting of the IEEE Photonics Society, 22nd, Proceedings, 266–267. IEEE.
- Vancouver
- 1.Debaes C, Artundo I, Heirman W, Loperena M, Van Campenhout J, Thienpont H. Architectural study of reconfigurable photonic networks-on-chip for multi-core processors. In: Annual meeting of the IEEE Photonics Society, 22nd, Proceedings. IEEE; 2009. p. 266–7.
- IEEE
- [1]C. Debaes, I. Artundo, W. Heirman, M. Loperena, J. Van Campenhout, and H. Thienpont, “Architectural study of reconfigurable photonic networks-on-chip for multi-core processors,” in Annual meeting of the IEEE Photonics Society, 22nd, Proceedings, Belek-Anatalya, Turkey, 2009, pp. 266–267.
@inproceedings{767773, abstract = {{Photonic Networks-on-Chip (NoCs) have become a promising route to interconnect processor cores on chip multiprocessors (CMP) in a power efficient way. Although several photonic NoC proposals exist, their use is limited to the communication of large data messages due to a relatively long set-up time for the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically to the evolving traffic situation. This way, long photonic channel set-up times can be tolerated which makes our approach more compatible in the context of shared-memory CMPs.}}, author = {{Debaes, Christof and Artundo, Iñigo and Heirman, Wim and Loperena, Mikel and Van Campenhout, Jan and Thienpont, Hugo}}, booktitle = {{Annual meeting of the IEEE Photonics Society, 22nd, Proceedings}}, keywords = {{Photonic switching systems,Parallel architectures,Reconfigurable architectures,Optical interconnections,Multiprocessor interconnection,Optical communication}}, language = {{eng}}, location = {{Belek-Anatalya, Turkey}}, pages = {{266--267}}, publisher = {{IEEE}}, title = {{Architectural study of reconfigurable photonic networks-on-chip for multi-core processors}}, year = {{2009}}, }