@article{7257138,
  abstract     = {Optimizing processors for (a) specific application(s) can substantially improve energy-efficiency. With the end of Dennard scaling, and the corresponding reduction in energy-efficiency gains from technology scaling, such approaches may become increasingly important. However, designing application-specific processors requires fast design space exploration tools to optimize for the targeted application(s). Analytical models can be a good fit for such design space exploration as they provide fast performance and power estimates and insight into the interaction between an application’s characteristics and the micro-architecture of a processor. Unfortunately, prior analytical models for superscalar out-of-order processors require micro-architecture dependent inputs, such as cache miss rates, branch miss rates and memory-level parallelism. This requires profiling the applications for each cache and branch predictor configuration of interest, which is far more time-consuming than evaluating the analytical performance models. In this work we present a micro-architecture independent profiler and associated analytical models that allow us to produce performance and power estimates across a large superscalar out-of-order processor design space almost instantaneously. We show that using a micro-architecture independent profile leads to a speedup of 300 compared to detailed simulation for our evaluated design space. Over a large design space, the model has a 9.3% average error for performance and a 4.3% average error for power, compared to detailed cycle-level simulation. The model is able to accurately determine the optimal processor configuration for different applications under power or performance constraints, and provides insight into performance through cycle stacks.},
  author       = {Van den Steen, Sam and Eyerman, Stijn and De Pestel, Sander and Mechri, Moncef and Carlson, Trevor and Black-Schaffer, David and Hagersten, Erik and Eeckhout, Lieven},
  issn         = {0018-9340},
  journal      = {IEEE TRANSACTIONS ON COMPUTERS},
  keywords     = {Micro-architecture,Analytical model,Performance,Power},
  language     = {eng},
  number       = {12},
  pages        = {3537--3551},
  publisher    = {IEEE},
  title        = {Analytical processor performance and power modeling using micro-architecture independent characteristics},
  url          = {http://dx.doi.org/10.1109/TC.2016.2547387},
  volume       = {65},
  year         = {2016},
}

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