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Shared resource aware scheduling on power-constrained tiled many-core processors

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Abstract
Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today’s power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases. In this paper, we propose a two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior.

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Citation

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MLA
Jha, Sudhanshu, et al. “Shared Resource Aware Scheduling on Power-Constrained Tiled Many-Core Processors.” Proceedings of the ACM International Conference on Computing Frontiers, 2016, pp. 365–68.
APA
Jha, S., Heirman, W., Falcon, A., Tubella, J., Gonzalez, A., & Eeckhout, L. (2016). Shared resource aware scheduling on power-constrained tiled many-core processors. Proceedings of the ACM International Conference on Computing Frontiers, 365–368.
Chicago author-date
Jha, Sudhanshu, Wim Heirman, Ayose Falcon, Jordi Tubella, Antonio Gonzalez, and Lieven Eeckhout. 2016. “Shared Resource Aware Scheduling on Power-Constrained Tiled Many-Core Processors.” In Proceedings of the ACM International Conference on Computing Frontiers, 365–68.
Chicago author-date (all authors)
Jha, Sudhanshu, Wim Heirman, Ayose Falcon, Jordi Tubella, Antonio Gonzalez, and Lieven Eeckhout. 2016. “Shared Resource Aware Scheduling on Power-Constrained Tiled Many-Core Processors.” In Proceedings of the ACM International Conference on Computing Frontiers, 365–368.
Vancouver
1.
Jha S, Heirman W, Falcon A, Tubella J, Gonzalez A, Eeckhout L. Shared resource aware scheduling on power-constrained tiled many-core processors. In: Proceedings of the ACM International Conference on Computing Frontiers. 2016. p. 365–8.
IEEE
[1]
S. Jha, W. Heirman, A. Falcon, J. Tubella, A. Gonzalez, and L. Eeckhout, “Shared resource aware scheduling on power-constrained tiled many-core processors,” in Proceedings of the ACM International Conference on Computing Frontiers, 2016, pp. 365–368.
@inproceedings{7245676,
  abstract     = {{Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today’s power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases. In this paper, we propose a two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior.}},
  author       = {{Jha, Sudhanshu and Heirman, Wim and Falcon, Ayose and Tubella, Jordi and Gonzalez, Antonio and Eeckhout, Lieven}},
  booktitle    = {{Proceedings of the ACM International Conference on Computing Frontiers}},
  language     = {{eng}},
  pages        = {{365--368}},
  title        = {{Shared resource aware scheduling on power-constrained tiled many-core processors}},
  year         = {{2016}},
}