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Efficient hardware debugging using parameterized FPGA reconfiguration

Alexandra Kourfali (UGent) and Dirk Stroobandt (UGent)
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Abstract
Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive func- tional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA’s routing infrastructure.
Keywords
TLUT, TCON, Reconfiguration, FPGA, Debugging, Parameterised Configuration, DCS

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Please use this url to cite or link to this publication:

Chicago
Kourfali, Alexandra, and Dirk Stroobandt. 2016. “Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration.” In 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 277–282. IEEE xplore.
APA
Kourfali, A., & Stroobandt, D. (2016). Efficient hardware debugging using parameterized FPGA reconfiguration. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (pp. 277–282). Presented at the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, IEEE xplore.
Vancouver
1.
Kourfali A, Stroobandt D. Efficient hardware debugging using parameterized FPGA reconfiguration. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. IEEE xplore; 2016. p. 277–82.
MLA
Kourfali, Alexandra, and Dirk Stroobandt. “Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration.” 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. IEEE xplore, 2016. 277–282. Print.
@inproceedings{7240436,
  abstract     = {Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive func- tional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA{\textquoteright}s routing infrastructure.},
  author       = {Kourfali, Alexandra and Stroobandt, Dirk},
  booktitle    = {2016 IEEE International Parallel and Distributed Processing Symposium Workshops},
  language     = {eng},
  location     = {Chicago, Illinois, USA},
  pages        = {277--282},
  publisher    = {IEEE xplore},
  title        = {Efficient hardware debugging using parameterized FPGA reconfiguration},
  url          = {http://dx.doi.org/10.1109/IPDPSW.2016.95},
  year         = {2016},
}

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