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A 16-bit Reconfigurable encryption processor for Pi-Cipher

Mohamed El-Hadedy, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt UGent and Kevin Skadron (2016) 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. p.162-171
abstract
This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher, implemented on an FPGA. Pi-Cipher is a nonce-based authenticated encryption cipher with associated data. The security of the Pi-Cipher relies on an ARX based permutation function, which is denoted as a Pi-function. The proposed ARX engine has been implemented in just 266 slices, which includes the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX engine allows for almost four times speedup in performance while consuming only 17% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
FPGA, Authenticated encryption, CAESAR, Cryptographic competitions, π-Cipher, micro-reconfiguration, parameterized configuration, TLUT
in
2016 IEEE International Parallel and Distributed Processing Symposium Workshops
pages
162 - 171
publisher
IEEE xplore
place of publication
Chicago, USA
conference name
2016 IEEE International Parallel and Distributed Processing Symposium Workshops
conference location
Chicago, USA
conference start
2016-05-23
conference end
2016-05-24
DOI
10.1109/IPDPSW.2016.27
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
7222721
handle
http://hdl.handle.net/1854/LU-7222721
date created
2016-05-20 16:55:52
date last changed
2017-01-02 09:53:29
@inproceedings{7222721,
  abstract     = {This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate, and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher, implemented on an FPGA. Pi-Cipher is a nonce-based authenticated encryption cipher with associated data. The security of the Pi-Cipher relies on an ARX based permutation function, which is denoted as a Pi-function. The proposed ARX engine has been implemented in just 266 slices, which includes the buffers of the input and the output. It can be clocked at 347 MHz. Also, in this paper, a message processor based on the proposed ARX engine is introduced. The message processor has been implemented in 1114 slices and it can be clocked at 250 MHz. The functionality of the proposed ARX engine was verified on the Xilinx Virtex-7. The new design of the ARX engine allows for almost four times speedup in performance while consuming only 17\% larger area than previously published work. We extend our message processor implementation by using parametrized reconfiguration technique after which an area reduction of 27 slices is observed.},
  author       = {El-Hadedy, Mohamed and Mihajloska, Hristina and Gligoroski, Danilo and Kulkarni, Amit and Stroobandt, Dirk and Skadron, Kevin},
  booktitle    = {2016 IEEE International Parallel and Distributed Processing Symposium Workshops},
  keyword      = {FPGA,Authenticated encryption,CAESAR,Cryptographic competitions,\ensuremath{\pi}-Cipher,micro-reconfiguration,parameterized configuration,TLUT},
  language     = {eng},
  location     = {Chicago, USA},
  pages        = {162--171},
  publisher    = {IEEE xplore},
  title        = {A 16-bit Reconfigurable encryption processor for Pi-Cipher},
  url          = {http://dx.doi.org/10.1109/IPDPSW.2016.27},
  year         = {2016},
}

Chicago
El-Hadedy, Mohamed, Hristina Mihajloska, Danilo Gligoroski, Amit Kulkarni, Dirk Stroobandt, and Kevin Skadron. 2016. “A 16-bit Reconfigurable Encryption Processor for Pi-Cipher.” In 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 162–171. Chicago, USA: IEEE xplore.
APA
El-Hadedy, M., Mihajloska, H., Gligoroski, D., Kulkarni, A., Stroobandt, D., & Skadron, K. (2016). A 16-bit Reconfigurable encryption processor for Pi-Cipher. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (pp. 162–171). Presented at the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, Chicago, USA: IEEE xplore.
Vancouver
1.
El-Hadedy M, Mihajloska H, Gligoroski D, Kulkarni A, Stroobandt D, Skadron K. A 16-bit Reconfigurable encryption processor for Pi-Cipher. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. Chicago, USA: IEEE xplore; 2016. p. 162–71.
MLA
El-Hadedy, Mohamed, Hristina Mihajloska, Danilo Gligoroski, et al. “A 16-bit Reconfigurable Encryption Processor for Pi-Cipher.” 2016 IEEE International Parallel and Distributed Processing Symposium Workshops. Chicago, USA: IEEE xplore, 2016. 162–171. Print.